Block RAM based design of 8-bit AES operation modes

Chi Wu Huang, Hong You Chen, Hsing Chang Yeh, Chi Jeng Chang

Research output: Contribution to journalConference article

2 Citations (Scopus)

Abstract

8-bit AES implementation was first proposed in 2006 as Application Specific Instruction Processer (ASIP).[1] It featured in low area design, for the increasing popular applications in wireless and embedded devices, based on the stored-program concept which the software programs run in an FPGA processor. This paper presents a direct FPGA implementation, in which the circuit areas varied depend on the algorithms and the implementing methods used. Our specific 8-bit implementation using three Block RAMs (BRAMs) achieves 88 slices in CFB/OFB mode and 134 slices in ECB mode which are better than or very close to 122 slices achieved by ASIP. The throughputs over 31 Mega bit per second (Mbps) are at least 14 times higher than 2.18 Mbps achieved by ASIP.

Original languageEnglish
Pages (from-to)2848-2852
Number of pages5
JournalProcedia Engineering
Volume29
DOIs
Publication statusPublished - 2012 Mar 22
Event2012 International Workshop on Information and Electronics Engineering, IWIEE 2012 - Harbin, China
Duration: 2012 Mar 102012 Mar 11

Fingerprint

Random access storage
Field programmable gate arrays (FPGA)
Throughput
Networks (circuits)

Keywords

  • AES
  • Block RAM(BRAM)
  • CFB
  • ECB
  • OFB

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Block RAM based design of 8-bit AES operation modes. / Huang, Chi Wu; Chen, Hong You; Yeh, Hsing Chang; Chang, Chi Jeng.

In: Procedia Engineering, Vol. 29, 22.03.2012, p. 2848-2852.

Research output: Contribution to journalConference article

Huang, Chi Wu ; Chen, Hong You ; Yeh, Hsing Chang ; Chang, Chi Jeng. / Block RAM based design of 8-bit AES operation modes. In: Procedia Engineering. 2012 ; Vol. 29. pp. 2848-2852.
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