Analysis of hot-carrier degradation in 0.25-μm surface-channel pMOSFET devices

Chuan H. Liu*, M. G. Chen, Shiang Huang-Lu, Y. J. Chang, K. Y. Fu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

5 Citations (Scopus)


Three conventional hot-carrier (HC) stress conditions (i.e. stress at Vgs ≈ Vth, Vgs ≈ Vds/2, and Vgs = Vds) have been studied for a quarter-micrometer level surface-channel pMOSFET devices. It is shown that stress at Vgs ≈ Vth results in the worst-case damage, in which a 'turn-around' behavior for device parameters (such as Idsat, Vth, and gm) has been observed (this is not seen in 0.35-μm or longer p-channel devices to the best of our knowledge). This turn-around behavior could be explained by a two-step degradation model (i.e. electron trapping and charge compensation between electron trapping and interface-state generation). Moreover, similar to long-channel pMOSFET devices though the dominant degradation mechanism is somewhat different, DC device lifetime for 0.25-μm pMOSFET devices should be evaluated using gate current as a predictor rather than substrate current that has been suggested by some researchers.

Original languageEnglish
Pages (from-to)82-85
Number of pages4
JournalInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings
Publication statusPublished - 1999
Externally publishedYes
EventProceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan
Duration: 1999 Jun 71999 Jun 10

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering


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