Analysis of hot-carrier degradation in 0.25-μm surface-channel pMOSFET devices

Chuan H. Liu, M. G. Chen, Shiang Huang-Lu, Y. J. Chang, K. Y. Fu

Research output: Contribution to journalConference article

4 Citations (Scopus)

Abstract

Three conventional hot-carrier (HC) stress conditions (i.e. stress at Vgs ≈ Vth, Vgs ≈ Vds/2, and Vgs = Vds) have been studied for a quarter-micrometer level surface-channel pMOSFET devices. It is shown that stress at Vgs ≈ Vth results in the worst-case damage, in which a 'turn-around' behavior for device parameters (such as Idsat, Vth, and gm) has been observed (this is not seen in 0.35-μm or longer p-channel devices to the best of our knowledge). This turn-around behavior could be explained by a two-step degradation model (i.e. electron trapping and charge compensation between electron trapping and interface-state generation). Moreover, similar to long-channel pMOSFET devices though the dominant degradation mechanism is somewhat different, DC device lifetime for 0.25-μm pMOSFET devices should be evaluated using gate current as a predictor rather than substrate current that has been suggested by some researchers.

Original languageEnglish
Pages (from-to)82-85
Number of pages4
JournalInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings
Publication statusPublished - 1999 Jan 1
EventProceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan
Duration: 1999 Jun 71999 Jun 10

Fingerprint

Hot carriers
degradation
Degradation
Electrons
Interface states
trapping
Substrates
micrometers
electrons
direct current
damage
life (durability)
predictions

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

Cite this

Analysis of hot-carrier degradation in 0.25-μm surface-channel pMOSFET devices. / Liu, Chuan H.; Chen, M. G.; Huang-Lu, Shiang; Chang, Y. J.; Fu, K. Y.

In: International Symposium on VLSI Technology, Systems, and Applications, Proceedings, 01.01.1999, p. 82-85.

Research output: Contribution to journalConference article

@article{f2a828dd2623458d893e85508cab2d4e,
title = "Analysis of hot-carrier degradation in 0.25-μm surface-channel pMOSFET devices",
abstract = "Three conventional hot-carrier (HC) stress conditions (i.e. stress at Vgs ≈ Vth, Vgs ≈ Vds/2, and Vgs = Vds) have been studied for a quarter-micrometer level surface-channel pMOSFET devices. It is shown that stress at Vgs ≈ Vth results in the worst-case damage, in which a 'turn-around' behavior for device parameters (such as Idsat, Vth, and gm) has been observed (this is not seen in 0.35-μm or longer p-channel devices to the best of our knowledge). This turn-around behavior could be explained by a two-step degradation model (i.e. electron trapping and charge compensation between electron trapping and interface-state generation). Moreover, similar to long-channel pMOSFET devices though the dominant degradation mechanism is somewhat different, DC device lifetime for 0.25-μm pMOSFET devices should be evaluated using gate current as a predictor rather than substrate current that has been suggested by some researchers.",
author = "Liu, {Chuan H.} and Chen, {M. G.} and Shiang Huang-Lu and Chang, {Y. J.} and Fu, {K. Y.}",
year = "1999",
month = "1",
day = "1",
language = "English",
pages = "82--85",
journal = "International Symposium on VLSI Technology, Systems, and Applications, Proceedings",
issn = "1524-766X",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - Analysis of hot-carrier degradation in 0.25-μm surface-channel pMOSFET devices

AU - Liu, Chuan H.

AU - Chen, M. G.

AU - Huang-Lu, Shiang

AU - Chang, Y. J.

AU - Fu, K. Y.

PY - 1999/1/1

Y1 - 1999/1/1

N2 - Three conventional hot-carrier (HC) stress conditions (i.e. stress at Vgs ≈ Vth, Vgs ≈ Vds/2, and Vgs = Vds) have been studied for a quarter-micrometer level surface-channel pMOSFET devices. It is shown that stress at Vgs ≈ Vth results in the worst-case damage, in which a 'turn-around' behavior for device parameters (such as Idsat, Vth, and gm) has been observed (this is not seen in 0.35-μm or longer p-channel devices to the best of our knowledge). This turn-around behavior could be explained by a two-step degradation model (i.e. electron trapping and charge compensation between electron trapping and interface-state generation). Moreover, similar to long-channel pMOSFET devices though the dominant degradation mechanism is somewhat different, DC device lifetime for 0.25-μm pMOSFET devices should be evaluated using gate current as a predictor rather than substrate current that has been suggested by some researchers.

AB - Three conventional hot-carrier (HC) stress conditions (i.e. stress at Vgs ≈ Vth, Vgs ≈ Vds/2, and Vgs = Vds) have been studied for a quarter-micrometer level surface-channel pMOSFET devices. It is shown that stress at Vgs ≈ Vth results in the worst-case damage, in which a 'turn-around' behavior for device parameters (such as Idsat, Vth, and gm) has been observed (this is not seen in 0.35-μm or longer p-channel devices to the best of our knowledge). This turn-around behavior could be explained by a two-step degradation model (i.e. electron trapping and charge compensation between electron trapping and interface-state generation). Moreover, similar to long-channel pMOSFET devices though the dominant degradation mechanism is somewhat different, DC device lifetime for 0.25-μm pMOSFET devices should be evaluated using gate current as a predictor rather than substrate current that has been suggested by some researchers.

UR - http://www.scopus.com/inward/record.url?scp=0032599254&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032599254&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0032599254

SP - 82

EP - 85

JO - International Symposium on VLSI Technology, Systems, and Applications, Proceedings

JF - International Symposium on VLSI Technology, Systems, and Applications, Proceedings

SN - 1524-766X

ER -