An X-band 9.75/10.6 GHz low-power phase-locked loop using 0.18-μm CMOS technology

Jeng Han Tsai, Chin Yi Hsu, Chia Hsiang Chao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)


An X-band 9.75/10.6 GHz fully-integrated low-power consumption phase-locked loop (PLL) is designed and fabricated on standard 0.18-μm CMOS process. Through the band control circuit of the voltage control oscillator (VCO) and mode control of the 7-bit divide-by-128∼255 multi-modulus frequency divider (MMD), the PLL output frequency of 9.75 GHz and 10.6 GHz is synthesized successfully with a reference source of 12.5 MHz. Utilizing the transformer feedback VCO and high speed true single phase clock (TSPC) based 2/3 cell divider, the PLL achieves low power consumption of 24 mW with good phase noise. The measured closed loop phase noise of the PLL at a frequency offset of 10 MHz is-116.24 dBc/Hz and-122.64 dBc/Hz with center of 9.75 GHz and 10.6 GHz, respectively.

Original languageEnglish
Title of host publicationEuropean Microwave Week 2015
Subtitle of host publication"Freedom Through Microwaves", EuMW 2015 - Conference Proceedings; 2015 10th European Microwave Integrated Circuits Conference Proceedings, EuMIC
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Electronic)9782874870408
Publication statusPublished - 2015 Dec 2
Event10th European Microwave Integrated Circuits Conference, EuMIC 2015 - Paris, France
Duration: 2015 Sept 72015 Sept 8

Publication series

NameEuropean Microwave Week 2015:


Other10th European Microwave Integrated Circuits Conference, EuMIC 2015


  • CMOS
  • Phase-locked loop (PLL)
  • X-band
  • radio frequency integration circuit (RFIC)

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering
  • Radiation


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