An X-band 9.75/10.6 GHz low-power phase-locked loop using 0.18-μm CMOS technology

Jeng-Han Tsai, Chin Yi Hsu, Chia Hsiang Chao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

An X-band 9.75/10.6 GHz fully-integrated low-power consumption phase-locked loop (PLL) is designed and fabricated on standard 0.18-μm CMOS process. Through the band control circuit of the voltage control oscillator (VCO) and mode control of the 7-bit divide-by-128∼255 multi-modulus frequency divider (MMD), the PLL output frequency of 9.75 GHz and 10.6 GHz is synthesized successfully with a reference source of 12.5 MHz. Utilizing the transformer feedback VCO and high speed true single phase clock (TSPC) based 2/3 cell divider, the PLL achieves low power consumption of 24 mW with good phase noise. The measured closed loop phase noise of the PLL at a frequency offset of 10 MHz is-116.24 dBc/Hz and-122.64 dBc/Hz with center of 9.75 GHz and 10.6 GHz, respectively.

Original languageEnglish
Title of host publicationEuropean Microwave Week 2015
Subtitle of host publication"Freedom Through Microwaves", EuMW 2015 - Conference Proceedings; 2015 10th European Microwave Integrated Circuits Conference Proceedings, EuMIC
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages238-241
Number of pages4
ISBN (Electronic)9782874870408
DOIs
Publication statusPublished - 2015 Dec 2
Event10th European Microwave Integrated Circuits Conference, EuMIC 2015 - Paris, France
Duration: 2015 Sep 72015 Sep 8

Publication series

NameEuropean Microwave Week 2015:

Other

Other10th European Microwave Integrated Circuits Conference, EuMIC 2015
CountryFrance
CityParis
Period15/9/715/9/8

Fingerprint

Phase locked loops
superhigh frequencies
CMOS
Phase noise
Voltage control
Electric power utilization
frequency dividers
voltage controlled oscillators
dividers
Feedback control
Clocks
transformers
clocks
oscillators
high speed
Networks (circuits)
output
electric potential
cells

Keywords

  • CMOS
  • Phase-locked loop (PLL)
  • X-band
  • radio frequency integration circuit (RFIC)

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering
  • Radiation

Cite this

Tsai, J-H., Hsu, C. Y., & Chao, C. H. (2015). An X-band 9.75/10.6 GHz low-power phase-locked loop using 0.18-μm CMOS technology. In European Microwave Week 2015: "Freedom Through Microwaves", EuMW 2015 - Conference Proceedings; 2015 10th European Microwave Integrated Circuits Conference Proceedings, EuMIC (pp. 238-241). [7345113] (European Microwave Week 2015:). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EuMIC.2015.7345113

An X-band 9.75/10.6 GHz low-power phase-locked loop using 0.18-μm CMOS technology. / Tsai, Jeng-Han; Hsu, Chin Yi; Chao, Chia Hsiang.

European Microwave Week 2015: "Freedom Through Microwaves", EuMW 2015 - Conference Proceedings; 2015 10th European Microwave Integrated Circuits Conference Proceedings, EuMIC. Institute of Electrical and Electronics Engineers Inc., 2015. p. 238-241 7345113 (European Microwave Week 2015:).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tsai, J-H, Hsu, CY & Chao, CH 2015, An X-band 9.75/10.6 GHz low-power phase-locked loop using 0.18-μm CMOS technology. in European Microwave Week 2015: "Freedom Through Microwaves", EuMW 2015 - Conference Proceedings; 2015 10th European Microwave Integrated Circuits Conference Proceedings, EuMIC., 7345113, European Microwave Week 2015:, Institute of Electrical and Electronics Engineers Inc., pp. 238-241, 10th European Microwave Integrated Circuits Conference, EuMIC 2015, Paris, France, 15/9/7. https://doi.org/10.1109/EuMIC.2015.7345113
Tsai J-H, Hsu CY, Chao CH. An X-band 9.75/10.6 GHz low-power phase-locked loop using 0.18-μm CMOS technology. In European Microwave Week 2015: "Freedom Through Microwaves", EuMW 2015 - Conference Proceedings; 2015 10th European Microwave Integrated Circuits Conference Proceedings, EuMIC. Institute of Electrical and Electronics Engineers Inc. 2015. p. 238-241. 7345113. (European Microwave Week 2015:). https://doi.org/10.1109/EuMIC.2015.7345113
Tsai, Jeng-Han ; Hsu, Chin Yi ; Chao, Chia Hsiang. / An X-band 9.75/10.6 GHz low-power phase-locked loop using 0.18-μm CMOS technology. European Microwave Week 2015: "Freedom Through Microwaves", EuMW 2015 - Conference Proceedings; 2015 10th European Microwave Integrated Circuits Conference Proceedings, EuMIC. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 238-241 (European Microwave Week 2015:).
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abstract = "An X-band 9.75/10.6 GHz fully-integrated low-power consumption phase-locked loop (PLL) is designed and fabricated on standard 0.18-μm CMOS process. Through the band control circuit of the voltage control oscillator (VCO) and mode control of the 7-bit divide-by-128∼255 multi-modulus frequency divider (MMD), the PLL output frequency of 9.75 GHz and 10.6 GHz is synthesized successfully with a reference source of 12.5 MHz. Utilizing the transformer feedback VCO and high speed true single phase clock (TSPC) based 2/3 cell divider, the PLL achieves low power consumption of 24 mW with good phase noise. The measured closed loop phase noise of the PLL at a frequency offset of 10 MHz is-116.24 dBc/Hz and-122.64 dBc/Hz with center of 9.75 GHz and 10.6 GHz, respectively.",
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AB - An X-band 9.75/10.6 GHz fully-integrated low-power consumption phase-locked loop (PLL) is designed and fabricated on standard 0.18-μm CMOS process. Through the band control circuit of the voltage control oscillator (VCO) and mode control of the 7-bit divide-by-128∼255 multi-modulus frequency divider (MMD), the PLL output frequency of 9.75 GHz and 10.6 GHz is synthesized successfully with a reference source of 12.5 MHz. Utilizing the transformer feedback VCO and high speed true single phase clock (TSPC) based 2/3 cell divider, the PLL achieves low power consumption of 24 mW with good phase noise. The measured closed loop phase noise of the PLL at a frequency offset of 10 MHz is-116.24 dBc/Hz and-122.64 dBc/Hz with center of 9.75 GHz and 10.6 GHz, respectively.

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