An ultra low-power 24 GHz Phase-lock-loop with low phase-noise VCO embedded in 0.18 μm CMOS process

Yu Hsuan Lin; Jeng Han Tsai; Yen Hung Kuo; Tian Wei Huang

An ultra low-power 24 GHz Phase-lock-loop with low phase-noise VCO embedded in 0.18 μm CMOS process

Yu Hsuan Lin^*, Jeng Han Tsai, Yen Hung Kuo, Tian Wei Huang

^*Corresponding author for this work

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

A 24 GHz 29.8 mW Phase-lock-loop using 0.18 m CMOS technology is presented in this paper. To achieve the low-power issue and low phase-noise performance, a transformer feedback voltage control oscillator and a cascoded divider of injection-locked frequency divider and current mode logic divider for low voltage and low power are implemented. The phase-lock-loop phase noise was measured by 122 dBc/Hz at 10 MHz offset with low supply voltage and equipped the locking range of 20.80-23.37 GHz. The PLL dissipate 29.8 mW (only 13.3 mW in VCO + ILFD) and occupies the total area of 0.39 mm ² without off-chip loop filter.

Original language	English
Title of host publication	Asia-Pacific Microwave Conference Proceedings, APMC 2011
Pages	1630-1633
Number of pages	4
Publication status	Published - 2011
Event	Asia-Pacific Microwave Conference, APMC 2011 - Melbourne, VIC, Australia Duration: 2011 Dec 5 → 2011 Dec 8

Publication series

Name	Asia-Pacific Microwave Conference Proceedings, APMC

Other

Other	Asia-Pacific Microwave Conference, APMC 2011
Country/Territory	Australia
City	Melbourne, VIC
Period	2011/12/05 → 2011/12/08

Keywords

CMOS
Injection-Locked Frequency Divider(ILFD)
Phase-Lock-Loop (PLL)
VCO

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

An ultra low-power 24 GHz Phase-lock-loop with low phase-noise VCO embedded in 0.18 μm CMOS process. / Lin, Yu Hsuan; Tsai, Jeng Han; Kuo, Yen Hung et al.
Asia-Pacific Microwave Conference Proceedings, APMC 2011. 2011. p. 1630-1633 6174079 (Asia-Pacific Microwave Conference Proceedings, APMC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lin, YH, Tsai, JH, Kuo, YH & Huang, TW 2011, An ultra low-power 24 GHz Phase-lock-loop with low phase-noise VCO embedded in 0.18 μm CMOS process. in Asia-Pacific Microwave Conference Proceedings, APMC 2011., 6174079, Asia-Pacific Microwave Conference Proceedings, APMC, pp. 1630-1633, Asia-Pacific Microwave Conference, APMC 2011, Melbourne, VIC, Australia, 2011/12/05.

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title = "An ultra low-power 24 GHz Phase-lock-loop with low phase-noise VCO embedded in 0.18 μm CMOS process",

abstract = "A 24 GHz 29.8 mW Phase-lock-loop using 0.18 m CMOS technology is presented in this paper. To achieve the low-power issue and low phase-noise performance, a transformer feedback voltage control oscillator and a cascoded divider of injection-locked frequency divider and current mode logic divider for low voltage and low power are implemented. The phase-lock-loop phase noise was measured by 122 dBc/Hz at 10 MHz offset with low supply voltage and equipped the locking range of 20.80-23.37 GHz. The PLL dissipate 29.8 mW (only 13.3 mW in VCO + ILFD) and occupies the total area of 0.39 mm 2 without off-chip loop filter.",

keywords = "CMOS, Injection-Locked Frequency Divider(ILFD), Phase-Lock-Loop (PLL), VCO",

author = "Lin, {Yu Hsuan} and Tsai, {Jeng Han} and Kuo, {Yen Hung} and Huang, {Tian Wei}",

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series = "Asia-Pacific Microwave Conference Proceedings, APMC",

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AU - Lin, Yu Hsuan

AU - Tsai, Jeng Han

AU - Kuo, Yen Hung

AU - Huang, Tian Wei

PY - 2011

Y1 - 2011

N2 - A 24 GHz 29.8 mW Phase-lock-loop using 0.18 m CMOS technology is presented in this paper. To achieve the low-power issue and low phase-noise performance, a transformer feedback voltage control oscillator and a cascoded divider of injection-locked frequency divider and current mode logic divider for low voltage and low power are implemented. The phase-lock-loop phase noise was measured by 122 dBc/Hz at 10 MHz offset with low supply voltage and equipped the locking range of 20.80-23.37 GHz. The PLL dissipate 29.8 mW (only 13.3 mW in VCO + ILFD) and occupies the total area of 0.39 mm 2 without off-chip loop filter.

AB - A 24 GHz 29.8 mW Phase-lock-loop using 0.18 m CMOS technology is presented in this paper. To achieve the low-power issue and low phase-noise performance, a transformer feedback voltage control oscillator and a cascoded divider of injection-locked frequency divider and current mode logic divider for low voltage and low power are implemented. The phase-lock-loop phase noise was measured by 122 dBc/Hz at 10 MHz offset with low supply voltage and equipped the locking range of 20.80-23.37 GHz. The PLL dissipate 29.8 mW (only 13.3 mW in VCO + ILFD) and occupies the total area of 0.39 mm 2 without off-chip loop filter.

KW - CMOS

KW - Injection-Locked Frequency Divider(ILFD)

KW - Phase-Lock-Loop (PLL)

KW - VCO

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An ultra low-power 24 GHz Phase-lock-loop with low phase-noise VCO embedded in 0.18 μm CMOS process

Abstract

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Keywords

ASJC Scopus subject areas

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