An ultra low-power 24 GHz Phase-lock-loop with low phase-noise VCO embedded in 0.18 μm CMOS process

Yu Hsuan Lin, Jeng Han Tsai, Yen Hung Kuo, Tian Wei Huang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

A 24 GHz 29.8 mW Phase-lock-loop using 0.18 m CMOS technology is presented in this paper. To achieve the low-power issue and low phase-noise performance, a transformer feedback voltage control oscillator and a cascoded divider of injection-locked frequency divider and current mode logic divider for low voltage and low power are implemented. The phase-lock-loop phase noise was measured by 122 dBc/Hz at 10 MHz offset with low supply voltage and equipped the locking range of 20.80-23.37 GHz. The PLL dissipate 29.8 mW (only 13.3 mW in VCO + ILFD) and occupies the total area of 0.39 mm 2 without off-chip loop filter.

Original languageEnglish
Title of host publicationAsia-Pacific Microwave Conference Proceedings, APMC 2011
Pages1630-1633
Number of pages4
Publication statusPublished - 2011 Dec 1
EventAsia-Pacific Microwave Conference, APMC 2011 - Melbourne, VIC, Australia
Duration: 2011 Dec 52011 Dec 8

Publication series

NameAsia-Pacific Microwave Conference Proceedings, APMC

Other

OtherAsia-Pacific Microwave Conference, APMC 2011
CountryAustralia
CityMelbourne, VIC
Period11/12/511/12/8

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Keywords

  • CMOS
  • Injection-Locked Frequency Divider(ILFD)
  • Phase-Lock-Loop (PLL)
  • VCO

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Lin, Y. H., Tsai, J. H., Kuo, Y. H., & Huang, T. W. (2011). An ultra low-power 24 GHz Phase-lock-loop with low phase-noise VCO embedded in 0.18 μm CMOS process. In Asia-Pacific Microwave Conference Proceedings, APMC 2011 (pp. 1630-1633). [6174079] (Asia-Pacific Microwave Conference Proceedings, APMC).