An FPGA implementation of chaotic and edge enhanced error diffusion

Chung Yen Su*, You Lin Sie

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)


Digital halftoning plays a central role in getting more observable grey-levels for either the innovative electronic paper or other less level devices. The hardware implementation of digital halftoning is, however, seldom fully explored. In this paper, we propose a novel implementation of digital halftoning by means of error diffusion. The proposed scheme not only can perform a new method called chaotic and edge enhanced error diffusion, but also can be reduced to perform the conventional Floyd-Steinberg error diffusion. Best of all, our new scheme can produce halftone images with lower worm-like artifacts and sharper image edges. This scheme is mainly composed of four components: gradientbased edge detection, chaotic threshold generation, edge enhanced quantization, and error diffusion. Each circuit design of the four components is illustrated for the first time. Besides, we demonstrate the hardware performance of our scheme by using a field programmable gate array (FPGA) chip to offer possibly further applications.

Original languageEnglish
Article number5606322
Pages (from-to)1755-1762
Number of pages8
JournalIEEE Transactions on Consumer Electronics
Issue number3
Publication statusPublished - 2010 Aug


  • Error diffusion
  • digital halftoning
  • edge enhancement
  • electronic paper
  • field programmable gate array

ASJC Scopus subject areas

  • Media Technology
  • Electrical and Electronic Engineering


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