An FPGA implementation of chaotic and edge enhanced error diffusion

Chung-Yen Su, You Lin Sie

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

Digital halftoning plays a central role in getting more observable grey-levels for either the innovative electronic paper or other less level devices. The hardware implementation of digital halftoning is, however, seldom fully explored. In this paper, we propose a novel implementation of digital halftoning by means of error diffusion. The proposed scheme not only can perform a new method called chaotic and edge enhanced error diffusion, but also can be reduced to perform the conventional Floyd-Steinberg error diffusion. Best of all, our new scheme can produce halftone images with lower worm-like artifacts and sharper image edges. This scheme is mainly composed of four components: gradientbased edge detection, chaotic threshold generation, edge enhanced quantization, and error diffusion. Each circuit design of the four components is illustrated for the first time. Besides, we demonstrate the hardware performance of our scheme by using a field programmable gate array (FPGA) chip to offer possibly further applications.

Original languageEnglish
Article number5606322
Pages (from-to)1755-1762
Number of pages8
JournalIEEE Transactions on Consumer Electronics
Volume56
Issue number3
DOIs
Publication statusPublished - 2010 Aug 1

Fingerprint

Field programmable gate arrays (FPGA)
Electronic paper
Hardware
Edge detection
Networks (circuits)

Keywords

  • Error diffusion
  • digital halftoning
  • edge enhancement
  • electronic paper
  • field programmable gate array

ASJC Scopus subject areas

  • Media Technology
  • Electrical and Electronic Engineering

Cite this

An FPGA implementation of chaotic and edge enhanced error diffusion. / Su, Chung-Yen; Sie, You Lin.

In: IEEE Transactions on Consumer Electronics, Vol. 56, No. 3, 5606322, 01.08.2010, p. 1755-1762.

Research output: Contribution to journalArticle

@article{87320e2c8e3c43ddb6ed8253999868fa,
title = "An FPGA implementation of chaotic and edge enhanced error diffusion",
abstract = "Digital halftoning plays a central role in getting more observable grey-levels for either the innovative electronic paper or other less level devices. The hardware implementation of digital halftoning is, however, seldom fully explored. In this paper, we propose a novel implementation of digital halftoning by means of error diffusion. The proposed scheme not only can perform a new method called chaotic and edge enhanced error diffusion, but also can be reduced to perform the conventional Floyd-Steinberg error diffusion. Best of all, our new scheme can produce halftone images with lower worm-like artifacts and sharper image edges. This scheme is mainly composed of four components: gradientbased edge detection, chaotic threshold generation, edge enhanced quantization, and error diffusion. Each circuit design of the four components is illustrated for the first time. Besides, we demonstrate the hardware performance of our scheme by using a field programmable gate array (FPGA) chip to offer possibly further applications.",
keywords = "Error diffusion, digital halftoning, edge enhancement, electronic paper, field programmable gate array",
author = "Chung-Yen Su and Sie, {You Lin}",
year = "2010",
month = "8",
day = "1",
doi = "10.1109/TCE.2010.5606322",
language = "English",
volume = "56",
pages = "1755--1762",
journal = "IEEE Transactions on Consumer Electronics",
issn = "0098-3063",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "3",

}

TY - JOUR

T1 - An FPGA implementation of chaotic and edge enhanced error diffusion

AU - Su, Chung-Yen

AU - Sie, You Lin

PY - 2010/8/1

Y1 - 2010/8/1

N2 - Digital halftoning plays a central role in getting more observable grey-levels for either the innovative electronic paper or other less level devices. The hardware implementation of digital halftoning is, however, seldom fully explored. In this paper, we propose a novel implementation of digital halftoning by means of error diffusion. The proposed scheme not only can perform a new method called chaotic and edge enhanced error diffusion, but also can be reduced to perform the conventional Floyd-Steinberg error diffusion. Best of all, our new scheme can produce halftone images with lower worm-like artifacts and sharper image edges. This scheme is mainly composed of four components: gradientbased edge detection, chaotic threshold generation, edge enhanced quantization, and error diffusion. Each circuit design of the four components is illustrated for the first time. Besides, we demonstrate the hardware performance of our scheme by using a field programmable gate array (FPGA) chip to offer possibly further applications.

AB - Digital halftoning plays a central role in getting more observable grey-levels for either the innovative electronic paper or other less level devices. The hardware implementation of digital halftoning is, however, seldom fully explored. In this paper, we propose a novel implementation of digital halftoning by means of error diffusion. The proposed scheme not only can perform a new method called chaotic and edge enhanced error diffusion, but also can be reduced to perform the conventional Floyd-Steinberg error diffusion. Best of all, our new scheme can produce halftone images with lower worm-like artifacts and sharper image edges. This scheme is mainly composed of four components: gradientbased edge detection, chaotic threshold generation, edge enhanced quantization, and error diffusion. Each circuit design of the four components is illustrated for the first time. Besides, we demonstrate the hardware performance of our scheme by using a field programmable gate array (FPGA) chip to offer possibly further applications.

KW - Error diffusion

KW - digital halftoning

KW - edge enhancement

KW - electronic paper

KW - field programmable gate array

UR - http://www.scopus.com/inward/record.url?scp=78149243753&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=78149243753&partnerID=8YFLogxK

U2 - 10.1109/TCE.2010.5606322

DO - 10.1109/TCE.2010.5606322

M3 - Article

AN - SCOPUS:78149243753

VL - 56

SP - 1755

EP - 1762

JO - IEEE Transactions on Consumer Electronics

JF - IEEE Transactions on Consumer Electronics

SN - 0098-3063

IS - 3

M1 - 5606322

ER -