An energy-efficiency split SAR ADC with floating capacitor and unit-cap bias-switching

Chien Hung Kuo; Han Chiang Lin

doi:10.1109/ISCE.2013.6570165

An energy-efficiency split SAR ADC with floating capacitor and unit-cap bias-switching

Chien Hung Kuo
, Han Chiang Lin

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents an energy-efficient and area-saving split successive approximation register analog-to-digital converter (SSAR ADC). By the use of the floating capacitor and V_cm sampling schemes, the DAC switched capacitors of the SSAR ADC can be reduced. With the use of the proposed unit-cap bias-switching, one more bit of output resolution can be improved. Comparing to the traditional SSAR ADC, the proposed SSAR can save 50.76% of chip area and efficiently reduce the consumption of switching energy.

Original language	English
Title of host publication	2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013
Pages	167-168
Number of pages	2
DOIs	https://doi.org/10.1109/ISCE.2013.6570165
Publication status	Published - 2013
Event	2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013 - Hsinchu, Taiwan Duration: 2013 Jun 3 → 2013 Jun 6

Publication series

Name	Proceedings of the International Symposium on Consumer Electronics, ISCE

Other

Other	2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013
Country/Territory	Taiwan
City	Hsinchu
Period	2013/06/03 → 2013/06/06

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

ASJC Scopus subject areas

General Engineering

Access to Document

10.1109/ISCE.2013.6570165

Cite this

An energy-efficiency split SAR ADC with floating capacitor and unit-cap bias-switching. / Kuo, Chien Hung; Lin, Han Chiang.
2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013. 2013. p. 167-168 6570165 (Proceedings of the International Symposium on Consumer Electronics, ISCE).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kuo, CH & Lin, HC 2013, An energy-efficiency split SAR ADC with floating capacitor and unit-cap bias-switching. in 2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013., 6570165, Proceedings of the International Symposium on Consumer Electronics, ISCE, pp. 167-168, 2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013, Hsinchu, Taiwan, 2013/06/03. https://doi.org/10.1109/ISCE.2013.6570165

@inproceedings{afc07400322d4fde9cfbfc17bcb3a781,

title = "An energy-efficiency split SAR ADC with floating capacitor and unit-cap bias-switching",

abstract = "This paper presents an energy-efficient and area-saving split successive approximation register analog-to-digital converter (SSAR ADC). By the use of the floating capacitor and Vcm sampling schemes, the DAC switched capacitors of the SSAR ADC can be reduced. With the use of the proposed unit-cap bias-switching, one more bit of output resolution can be improved. Comparing to the traditional SSAR ADC, the proposed SSAR can save 50.76\% of chip area and efficiently reduce the consumption of switching energy.",

author = "Kuo, \{Chien Hung\} and Lin, \{Han Chiang\}",

year = "2013",

doi = "10.1109/ISCE.2013.6570165",

language = "English",

isbn = "9781467361996",

series = "Proceedings of the International Symposium on Consumer Electronics, ISCE",

pages = "167--168",

booktitle = "2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013",

note = "2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013 ; Conference date: 03-06-2013 Through 06-06-2013",

}

TY - GEN

T1 - An energy-efficiency split SAR ADC with floating capacitor and unit-cap bias-switching

AU - Kuo, Chien Hung

AU - Lin, Han Chiang

PY - 2013

Y1 - 2013

N2 - This paper presents an energy-efficient and area-saving split successive approximation register analog-to-digital converter (SSAR ADC). By the use of the floating capacitor and Vcm sampling schemes, the DAC switched capacitors of the SSAR ADC can be reduced. With the use of the proposed unit-cap bias-switching, one more bit of output resolution can be improved. Comparing to the traditional SSAR ADC, the proposed SSAR can save 50.76% of chip area and efficiently reduce the consumption of switching energy.

AB - This paper presents an energy-efficient and area-saving split successive approximation register analog-to-digital converter (SSAR ADC). By the use of the floating capacitor and Vcm sampling schemes, the DAC switched capacitors of the SSAR ADC can be reduced. With the use of the proposed unit-cap bias-switching, one more bit of output resolution can be improved. Comparing to the traditional SSAR ADC, the proposed SSAR can save 50.76% of chip area and efficiently reduce the consumption of switching energy.

UR - https://www.scopus.com/pages/publications/84883525800

UR - https://www.scopus.com/pages/publications/84883525800#tab=citedBy

U2 - 10.1109/ISCE.2013.6570165

DO - 10.1109/ISCE.2013.6570165

M3 - Conference contribution

AN - SCOPUS:84883525800

SN - 9781467361996

T3 - Proceedings of the International Symposium on Consumer Electronics, ISCE

SP - 167

EP - 168

BT - 2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013

T2 - 2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013

Y2 - 3 June 2013 through 6 June 2013

ER -

An energy-efficiency split SAR ADC with floating capacitor and unit-cap bias-switching

Abstract

Publication series

Other

UN SDGs

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this