TY - GEN
T1 - An energy-efficiency split SAR ADC with floating capacitor and unit-cap bias-switching
AU - Kuo, Chien Hung
AU - Lin, Han Chiang
PY - 2013
Y1 - 2013
N2 - This paper presents an energy-efficient and area-saving split successive approximation register analog-to-digital converter (SSAR ADC). By the use of the floating capacitor and Vcm sampling schemes, the DAC switched capacitors of the SSAR ADC can be reduced. With the use of the proposed unit-cap bias-switching, one more bit of output resolution can be improved. Comparing to the traditional SSAR ADC, the proposed SSAR can save 50.76% of chip area and efficiently reduce the consumption of switching energy.
AB - This paper presents an energy-efficient and area-saving split successive approximation register analog-to-digital converter (SSAR ADC). By the use of the floating capacitor and Vcm sampling schemes, the DAC switched capacitors of the SSAR ADC can be reduced. With the use of the proposed unit-cap bias-switching, one more bit of output resolution can be improved. Comparing to the traditional SSAR ADC, the proposed SSAR can save 50.76% of chip area and efficiently reduce the consumption of switching energy.
UR - http://www.scopus.com/inward/record.url?scp=84883525800&partnerID=8YFLogxK
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U2 - 10.1109/ISCE.2013.6570165
DO - 10.1109/ISCE.2013.6570165
M3 - Conference contribution
AN - SCOPUS:84883525800
SN - 9781467361996
T3 - Proceedings of the International Symposium on Consumer Electronics, ISCE
SP - 167
EP - 168
BT - 2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013
T2 - 2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013
Y2 - 3 June 2013 through 6 June 2013
ER -
