An energy-efficiency split SAR ADC with floating capacitor and unit-cap bias-switching

Chien Hung Kuo, Han Chiang Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents an energy-efficient and area-saving split successive approximation register analog-to-digital converter (SSAR ADC). By the use of the floating capacitor and Vcm sampling schemes, the DAC switched capacitors of the SSAR ADC can be reduced. With the use of the proposed unit-cap bias-switching, one more bit of output resolution can be improved. Comparing to the traditional SSAR ADC, the proposed SSAR can save 50.76% of chip area and efficiently reduce the consumption of switching energy.

Original languageEnglish
Title of host publication2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013
Pages167-168
Number of pages2
DOIs
Publication statusPublished - 2013 Sep 11
Event2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013 - Hsinchu, Taiwan
Duration: 2013 Jun 32013 Jun 6

Publication series

NameProceedings of the International Symposium on Consumer Electronics, ISCE

Other

Other2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013
CountryTaiwan
CityHsinchu
Period13/6/313/6/6

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Kuo, C. H., & Lin, H. C. (2013). An energy-efficiency split SAR ADC with floating capacitor and unit-cap bias-switching. In 2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013 (pp. 167-168). [6570165] (Proceedings of the International Symposium on Consumer Electronics, ISCE). https://doi.org/10.1109/ISCE.2013.6570165