An efficient VLSI architecture for multi-channel spike sorting using a generalized hebbian algorithm

Ying Lun Chen, Wen Jyi Hwang, Chi En Ke

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

Original languageEnglish
Pages (from-to)19830-19851
Number of pages22
JournalSensors (Switzerland)
Volume15
Issue number8
DOIs
Publication statusPublished - 2015 Aug 13

Keywords

  • Brain machine interface
  • Spike sorting
  • VLSI

ASJC Scopus subject areas

  • Analytical Chemistry
  • Biochemistry
  • Atomic and Molecular Physics, and Optics
  • Instrumentation
  • Electrical and Electronic Engineering

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