An efficient pipelined architecture for fast competitive learning

Hui Ya Li, Chia Lung Hung, Wen Jyi Hwang

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)

    Abstract

    This paper presents a novel pipelined architecture for fast competitive learning (CL). It is used as a hardware accelerator in a system on programmable chip (SOPC) for reducing the computational time. In the architecture, a novel codeword swapping scheme is adopted so that both neuron competition processes for different training vectors can be operated concurrently. The neuron updating process is based on a hardware divider with simple table lookup operations. The divider performs finite precision calculation for area cost reduction at the expense of slight degradation in training performance. Experimental results show that the CPU time is lower than that of other hardware or software implementations running the CL training program with or without the support of custom hardware.

    Original languageEnglish
    Title of host publicationAlgorithms and Architectures for Parallel Processing - 10th International Conference, ICA3PP 2010, Workshops
    Pages381-390
    Number of pages10
    EditionPART 2
    DOIs
    Publication statusPublished - 2010 Dec 1
    Event10th International Conference Algorithms and Architectures for Parallel Processing, ICA3PP 2010 - Busan, Korea, Republic of
    Duration: 2010 May 212010 May 23

    Publication series

    NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
    NumberPART 2
    Volume6082 LNCS
    ISSN (Print)0302-9743
    ISSN (Electronic)1611-3349

    Other

    Other10th International Conference Algorithms and Architectures for Parallel Processing, ICA3PP 2010
    CountryKorea, Republic of
    CityBusan
    Period10/5/2110/5/23

    ASJC Scopus subject areas

    • Theoretical Computer Science
    • Computer Science(all)

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