An efficient heuristic for minimizing maximum lateness on parallel batch machines

Tsung Che Chiang, Hsueh Chien Cheng, Li Chen Fu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Batch machines are common in many complex manufacturing systems like wafer fabrication facilities. They are characterized by multiple capacity and long processing times, and thus scheduling of them is important for raising the performance of the entire system. In this paper, we address the identical parallel batch machine scheduling problem considering incompatible job families and dynamic job arrivals. A local search-based heuristic is proposed to minimize maximum lateness. Performance of the proposed heuristic is compared with a state-of-the-art genetic algorithm-based approach, and the experimental results show that our approach is better than the benchmark approach in terms of both solution quality and computational efficiency.

Original languageEnglish
Title of host publicationProceedings - 8th International Conference on Intelligent Systems Design and Applications, ISDA 2008
Pages621-627
Number of pages7
DOIs
Publication statusPublished - 2008 Dec 1
Event8th International Conference on Intelligent Systems Design and Applications, ISDA 2008 - Kaohsiung, Taiwan
Duration: 2008 Nov 262008 Nov 28

Publication series

NameProceedings - 8th International Conference on Intelligent Systems Design and Applications, ISDA 2008
Volume2

Other

Other8th International Conference on Intelligent Systems Design and Applications, ISDA 2008
CountryTaiwan
CityKaohsiung
Period08/11/2608/11/28

Fingerprint

Scheduling
Computational efficiency
Genetic algorithms
Fabrication
Processing

ASJC Scopus subject areas

  • Artificial Intelligence
  • Control and Systems Engineering

Cite this

Chiang, T. C., Cheng, H. C., & Fu, L. C. (2008). An efficient heuristic for minimizing maximum lateness on parallel batch machines. In Proceedings - 8th International Conference on Intelligent Systems Design and Applications, ISDA 2008 (pp. 621-627). [4696403] (Proceedings - 8th International Conference on Intelligent Systems Design and Applications, ISDA 2008; Vol. 2). https://doi.org/10.1109/ISDA.2008.73

An efficient heuristic for minimizing maximum lateness on parallel batch machines. / Chiang, Tsung Che; Cheng, Hsueh Chien; Fu, Li Chen.

Proceedings - 8th International Conference on Intelligent Systems Design and Applications, ISDA 2008. 2008. p. 621-627 4696403 (Proceedings - 8th International Conference on Intelligent Systems Design and Applications, ISDA 2008; Vol. 2).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Chiang, TC, Cheng, HC & Fu, LC 2008, An efficient heuristic for minimizing maximum lateness on parallel batch machines. in Proceedings - 8th International Conference on Intelligent Systems Design and Applications, ISDA 2008., 4696403, Proceedings - 8th International Conference on Intelligent Systems Design and Applications, ISDA 2008, vol. 2, pp. 621-627, 8th International Conference on Intelligent Systems Design and Applications, ISDA 2008, Kaohsiung, Taiwan, 08/11/26. https://doi.org/10.1109/ISDA.2008.73
Chiang TC, Cheng HC, Fu LC. An efficient heuristic for minimizing maximum lateness on parallel batch machines. In Proceedings - 8th International Conference on Intelligent Systems Design and Applications, ISDA 2008. 2008. p. 621-627. 4696403. (Proceedings - 8th International Conference on Intelligent Systems Design and Applications, ISDA 2008). https://doi.org/10.1109/ISDA.2008.73
Chiang, Tsung Che ; Cheng, Hsueh Chien ; Fu, Li Chen. / An efficient heuristic for minimizing maximum lateness on parallel batch machines. Proceedings - 8th International Conference on Intelligent Systems Design and Applications, ISDA 2008. 2008. pp. 621-627 (Proceedings - 8th International Conference on Intelligent Systems Design and Applications, ISDA 2008).
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