An efficient hardware circuit for spike sorting based on competitive learning networks

INIS

• learning 100%
• detection 100%
• classification 100%
• sorting 100%
• extraction 75%
• architecture 75%
• power 50%
• implementation 50%
• operation 50%
• performance 25%
• applications 25%
• vectors 25%
• cost 25%
• algorithms 25%
• neural networks 25%
• calculation methods 25%
• nonlinear problems 25%
• peaks 25%
• integrated circuits 25%
• energy operators 25%

Engineering

• Feature Extraction 100%
• Energy Dissipation 66%
• Experimental Result 33%
• Success Rate 33%
• Chip Area 33%
• Application Specific Integrated Circuit 33%
• Spike Detection 33%
• VLSI Circuits 33%
• Multichannel 33%
• Realization 33%
• Feature Vector 33%
• Hardware Cost 33%

Computer Science

• Energy Operator 33%