An efficient FPGA-based architecture for convolutional neural networks

Wen Jyi Hwang; Yun Jie Jhang; Tsung Ming Tai

doi:10.1109/TSP.2017.8076054

An efficient FPGA-based architecture for convolutional neural networks

Wen Jyi Hwang, Yun Jie Jhang, Tsung Ming Tai

Department of Computer Science and Information Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

The goal of this paper is to implement an efficient FPGA-based hardware architectures for the design of fast artificial vision systems. The proposed architecture is capable of performing classification operations of a Convolutional Neural Network (CNN) in realtime. To show the effectiveness of the architecture, some design examples such as hand posture recognition, character recognition, and face recognition are provided. Experimental results show that the proposed architecture is well suited for embedded artificial computer vision systems requiring high portability, high computational speed, and accurate classification.

Original language	English
Title of host publication	2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017
Editors	Norbert Herencsar
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	582-588
Number of pages	7
ISBN (Electronic)	9781509039821
DOIs	https://doi.org/10.1109/TSP.2017.8076054
Publication status	Published - 2017 Oct 19
Event	40th International Conference on Telecommunications and Signal Processing, TSP 2017 - Barcelona, Spain Duration: 2017 Jul 5 → 2017 Jul 7

Publication series

Name	2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017
Volume	2017-January

Other

Other	40th International Conference on Telecommunications and Signal Processing, TSP 2017
Country/Territory	Spain
City	Barcelona
Period	2017/07/05 → 2017/07/07

Keywords

Artificial vision systems
Convolutional neural networks
Field programmable gate array
Hardware architecture
Pipeline operations

ASJC Scopus subject areas

Computer Networks and Communications
Signal Processing

Access to Document

10.1109/TSP.2017.8076054

Cite this

Hwang, W. J., Jhang, Y. J., & Tai, T. M. (2017). An efficient FPGA-based architecture for convolutional neural networks. In N. Herencsar (Ed.), 2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017 (pp. 582-588). (2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017; Vol. 2017-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/TSP.2017.8076054

An efficient FPGA-based architecture for convolutional neural networks. / Hwang, Wen Jyi; Jhang, Yun Jie; Tai, Tsung Ming.
2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017. ed. / Norbert Herencsar. Institute of Electrical and Electronics Engineers Inc., 2017. p. 582-588 (2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017; Vol. 2017-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hwang, WJ, Jhang, YJ & Tai, TM 2017, An efficient FPGA-based architecture for convolutional neural networks. in N Herencsar (ed.), 2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017. 2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017, vol. 2017-January, Institute of Electrical and Electronics Engineers Inc., pp. 582-588, 40th International Conference on Telecommunications and Signal Processing, TSP 2017, Barcelona, Spain, 2017/07/05. https://doi.org/10.1109/TSP.2017.8076054

Hwang WJ, Jhang YJ, Tai TM. An efficient FPGA-based architecture for convolutional neural networks. In Herencsar N, editor, 2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 582-588. (2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017). doi: 10.1109/TSP.2017.8076054

Hwang, Wen Jyi ; Jhang, Yun Jie ; Tai, Tsung Ming. / An efficient FPGA-based architecture for convolutional neural networks. 2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017. editor / Norbert Herencsar. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 582-588 (2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017).

@inproceedings{444bddfa273a4cbeb3d2971430ff2be9,

title = "An efficient FPGA-based architecture for convolutional neural networks",

abstract = "The goal of this paper is to implement an efficient FPGA-based hardware architectures for the design of fast artificial vision systems. The proposed architecture is capable of performing classification operations of a Convolutional Neural Network (CNN) in realtime. To show the effectiveness of the architecture, some design examples such as hand posture recognition, character recognition, and face recognition are provided. Experimental results show that the proposed architecture is well suited for embedded artificial computer vision systems requiring high portability, high computational speed, and accurate classification.",

keywords = "Artificial vision systems, Convolutional neural networks, Field programmable gate array, Hardware architecture, Pipeline operations",

author = "Hwang, {Wen Jyi} and Jhang, {Yun Jie} and Tai, {Tsung Ming}",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 40th International Conference on Telecommunications and Signal Processing, TSP 2017 ; Conference date: 05-07-2017 Through 07-07-2017",

year = "2017",

month = oct,

day = "19",

doi = "10.1109/TSP.2017.8076054",

language = "English",

series = "2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "582--588",

editor = "Norbert Herencsar",

booktitle = "2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017",

}

TY - GEN

T1 - An efficient FPGA-based architecture for convolutional neural networks

AU - Hwang, Wen Jyi

AU - Jhang, Yun Jie

AU - Tai, Tsung Ming

PY - 2017/10/19

Y1 - 2017/10/19

N2 - The goal of this paper is to implement an efficient FPGA-based hardware architectures for the design of fast artificial vision systems. The proposed architecture is capable of performing classification operations of a Convolutional Neural Network (CNN) in realtime. To show the effectiveness of the architecture, some design examples such as hand posture recognition, character recognition, and face recognition are provided. Experimental results show that the proposed architecture is well suited for embedded artificial computer vision systems requiring high portability, high computational speed, and accurate classification.

AB - The goal of this paper is to implement an efficient FPGA-based hardware architectures for the design of fast artificial vision systems. The proposed architecture is capable of performing classification operations of a Convolutional Neural Network (CNN) in realtime. To show the effectiveness of the architecture, some design examples such as hand posture recognition, character recognition, and face recognition are provided. Experimental results show that the proposed architecture is well suited for embedded artificial computer vision systems requiring high portability, high computational speed, and accurate classification.

KW - Artificial vision systems

KW - Convolutional neural networks

KW - Field programmable gate array

KW - Hardware architecture

KW - Pipeline operations

UR - http://www.scopus.com/inward/record.url?scp=85043276060&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85043276060&partnerID=8YFLogxK

U2 - 10.1109/TSP.2017.8076054

DO - 10.1109/TSP.2017.8076054

M3 - Conference contribution

AN - SCOPUS:85043276060

T3 - 2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017

SP - 582

EP - 588

BT - 2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017

A2 - Herencsar, Norbert

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 40th International Conference on Telecommunications and Signal Processing, TSP 2017

Y2 - 5 July 2017 through 7 July 2017

ER -

An efficient FPGA-based architecture for convolutional neural networks

Abstract

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Keywords

ASJC Scopus subject areas

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