An efficient FPGA-based architecture for convolutional neural networks

Wen-Jyi Hwang, Yun Jie Jhang, Tsung Ming Tai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The goal of this paper is to implement an efficient FPGA-based hardware architectures for the design of fast artificial vision systems. The proposed architecture is capable of performing classification operations of a Convolutional Neural Network (CNN) in realtime. To show the effectiveness of the architecture, some design examples such as hand posture recognition, character recognition, and face recognition are provided. Experimental results show that the proposed architecture is well suited for embedded artificial computer vision systems requiring high portability, high computational speed, and accurate classification.

Original languageEnglish
Title of host publication2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017
EditorsNorbert Herencsar
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages582-588
Number of pages7
ISBN (Electronic)9781509039821
DOIs
Publication statusPublished - 2017 Oct 19
Event40th International Conference on Telecommunications and Signal Processing, TSP 2017 - Barcelona, Spain
Duration: 2017 Jul 52017 Jul 7

Publication series

Name2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017
Volume2017-January

Other

Other40th International Conference on Telecommunications and Signal Processing, TSP 2017
CountrySpain
CityBarcelona
Period17/7/517/7/7

Fingerprint

Computer vision
Field programmable gate arrays (FPGA)
Palmprint recognition
Neural networks
Character recognition
Face recognition
Hardware

Keywords

  • Artificial vision systems
  • Convolutional neural networks
  • Field programmable gate array
  • Hardware architecture
  • Pipeline operations

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Signal Processing

Cite this

Hwang, W-J., Jhang, Y. J., & Tai, T. M. (2017). An efficient FPGA-based architecture for convolutional neural networks. In N. Herencsar (Ed.), 2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017 (pp. 582-588). (2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017; Vol. 2017-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/TSP.2017.8076054

An efficient FPGA-based architecture for convolutional neural networks. / Hwang, Wen-Jyi; Jhang, Yun Jie; Tai, Tsung Ming.

2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017. ed. / Norbert Herencsar. Institute of Electrical and Electronics Engineers Inc., 2017. p. 582-588 (2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017; Vol. 2017-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hwang, W-J, Jhang, YJ & Tai, TM 2017, An efficient FPGA-based architecture for convolutional neural networks. in N Herencsar (ed.), 2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017. 2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017, vol. 2017-January, Institute of Electrical and Electronics Engineers Inc., pp. 582-588, 40th International Conference on Telecommunications and Signal Processing, TSP 2017, Barcelona, Spain, 17/7/5. https://doi.org/10.1109/TSP.2017.8076054
Hwang W-J, Jhang YJ, Tai TM. An efficient FPGA-based architecture for convolutional neural networks. In Herencsar N, editor, 2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 582-588. (2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017). https://doi.org/10.1109/TSP.2017.8076054
Hwang, Wen-Jyi ; Jhang, Yun Jie ; Tai, Tsung Ming. / An efficient FPGA-based architecture for convolutional neural networks. 2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017. editor / Norbert Herencsar. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 582-588 (2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017).
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