All-nMOS Power-Rail ESD Clamp Circuit with Compact Area and Low Leakage

ICs are susceptible to breakage due to electrostatic discharge (ESD), making ESD protection circuits necessary for ICs. In some applications, internal circuits may adopt an all n-type transistor design. In such cases, the ESD protection circuit should only use n-type transistors to reduce the number of process masks required. This work proposes both a basic and an improved design for an all-nMOS power-rail ESD clamp. The improved design uses a current mirror circuit and nMOS string to reduce chip area and leakage, respectively. These ESD protection circuits have been implemented and validated in a 0.18-μ m CMOS process. The proposed designs are cost-effective and offer higher ESD robustness for practical applications.