Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO 2 gate stack

C. H. Cheng; K. I. Chou; Albert Chin

doi:10.1016/j.sse.2013.02.003

Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO ₂ gate stack

C. H. Cheng^*
, K. I. Chou
, Albert Chin

^*Corresponding author for this work

Department of Mechatronic Engineering

Research output: Contribution to journal › Article › peer-review

3 Citations (Scopus)

Abstract

We report a gate-first TiLaO/CeO₂ n-MOSFET with an equivalent oxide thickness (EOT) of only 0.56 nm and threshold voltage (V_t) of 0.31 V. This small EOT MOSFET was achieved by employing high-κ CeO ₂ interfacial layer with high bond enthalpy (795 kJ/mol) to replace low-κ SiO₂ with close bond enthalpy (800 kJ/mol). The cerium silicate can aggressively scale EOT down to sub-0.6-nm EOT region without increasing gate leakage, which is urgently needed for 16 nm technology node.

Original language	English
Pages (from-to)	111-114
Number of pages	4
Journal	Solid-State Electronics
Volume	82
DOIs	https://doi.org/10.1016/j.sse.2013.02.003
Publication status	Published - 2013

Keywords

CeO
Gate first
Small EOT
TiLaO

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Access to Document

10.1016/j.sse.2013.02.003

Cite this

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title = "Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO 2 gate stack",

abstract = "We report a gate-first TiLaO/CeO2 n-MOSFET with an equivalent oxide thickness (EOT) of only 0.56 nm and threshold voltage (Vt) of 0.31 V. This small EOT MOSFET was achieved by employing high-κ CeO 2 interfacial layer with high bond enthalpy (795 kJ/mol) to replace low-κ SiO2 with close bond enthalpy (800 kJ/mol). The cerium silicate can aggressively scale EOT down to sub-0.6-nm EOT region without increasing gate leakage, which is urgently needed for 16 nm technology node.",

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pages = "111--114",

journal = "Solid-State Electronics",

issn = "0038-1101",

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T1 - Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO 2 gate stack

AU - Cheng, C. H.

AU - Chou, K. I.

AU - Chin, Albert

PY - 2013

Y1 - 2013

N2 - We report a gate-first TiLaO/CeO2 n-MOSFET with an equivalent oxide thickness (EOT) of only 0.56 nm and threshold voltage (Vt) of 0.31 V. This small EOT MOSFET was achieved by employing high-κ CeO 2 interfacial layer with high bond enthalpy (795 kJ/mol) to replace low-κ SiO2 with close bond enthalpy (800 kJ/mol). The cerium silicate can aggressively scale EOT down to sub-0.6-nm EOT region without increasing gate leakage, which is urgently needed for 16 nm technology node.

AB - We report a gate-first TiLaO/CeO2 n-MOSFET with an equivalent oxide thickness (EOT) of only 0.56 nm and threshold voltage (Vt) of 0.31 V. This small EOT MOSFET was achieved by employing high-κ CeO 2 interfacial layer with high bond enthalpy (795 kJ/mol) to replace low-κ SiO2 with close bond enthalpy (800 kJ/mol). The cerium silicate can aggressively scale EOT down to sub-0.6-nm EOT region without increasing gate leakage, which is urgently needed for 16 nm technology node.

KW - CeO

KW - Gate first

KW - Small EOT

KW - TiLaO

UR - https://www.scopus.com/pages/publications/84875136427

UR - https://www.scopus.com/pages/publications/84875136427#tab=citedBy

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DO - 10.1016/j.sse.2013.02.003

M3 - Article

AN - SCOPUS:84875136427

SN - 0038-1101

VL - 82

SP - 111

EP - 114

JO - Solid-State Electronics

JF - Solid-State Electronics

ER -