Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO 2 gate stack

Chun-Hu Cheng, K. I. Chou, Albert Chin

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

We report a gate-first TiLaO/CeO2 n-MOSFET with an equivalent oxide thickness (EOT) of only 0.56 nm and threshold voltage (Vt) of 0.31 V. This small EOT MOSFET was achieved by employing high-κ CeO 2 interfacial layer with high bond enthalpy (795 kJ/mol) to replace low-κ SiO2 with close bond enthalpy (800 kJ/mol). The cerium silicate can aggressively scale EOT down to sub-0.6-nm EOT region without increasing gate leakage, which is urgently needed for 16 nm technology node.

Original languageEnglish
Pages (from-to)111-114
Number of pages4
JournalSolid-State Electronics
Volume82
DOIs
Publication statusPublished - 2013 Mar 25

Fingerprint

Oxides
field effect transistors
oxides
Enthalpy
enthalpy
Cerium
Silicates
cerium
Threshold voltage
threshold voltage
silicates
leakage
electric potential

Keywords

  • CeO
  • Gate first
  • Small EOT
  • TiLaO

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

Cite this

Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO 2 gate stack. / Cheng, Chun-Hu; Chou, K. I.; Chin, Albert.

In: Solid-State Electronics, Vol. 82, 25.03.2013, p. 111-114.

Research output: Contribution to journalArticle

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