TY - GEN
T1 - Achieving high-scalability negative capacitance FETs with uniform Sub-35 mV/dec switch using dopant-free hafnium oxide and gate strain
AU - Fan, Chia Chi
AU - Cheng, Chun Hu
AU - Tu, Chun Yuan
AU - Liu, Chien
AU - Chen, Wan Hsin
AU - Chang, Tun Jen
AU - Chang, Chun Yen
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/10/25
Y1 - 2018/10/25
N2 - For the first time, we successfully demonstrated that the 4-nm-thick dopant-free HfO2 NCFETs using gate strain can implement an energy-efficient switch of a low gate overdrive voltage and a nearly hysteresis-free sub-40 mV/dec swing. The gate strain favorably rearranges oxygen vacancies and boosts orthorhombic phase transition. Furthermore, the dopant-free HfO2 NCFET can be further improved by in-situ nitridation process. The 4-nm-thick nitrided HfO2 NCFETs achieve a steep symmetric sub-35 mV/dec switch, a sustained sub-40 mV/dec SS distribution, and excellent stress immunity during NC switch. The high-scalability and dopant-free NCFET shows the great potential for the application of future highly-scaled 3D CMOS technology.
AB - For the first time, we successfully demonstrated that the 4-nm-thick dopant-free HfO2 NCFETs using gate strain can implement an energy-efficient switch of a low gate overdrive voltage and a nearly hysteresis-free sub-40 mV/dec swing. The gate strain favorably rearranges oxygen vacancies and boosts orthorhombic phase transition. Furthermore, the dopant-free HfO2 NCFET can be further improved by in-situ nitridation process. The 4-nm-thick nitrided HfO2 NCFETs achieve a steep symmetric sub-35 mV/dec switch, a sustained sub-40 mV/dec SS distribution, and excellent stress immunity during NC switch. The high-scalability and dopant-free NCFET shows the great potential for the application of future highly-scaled 3D CMOS technology.
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U2 - 10.1109/VLSIT.2018.8510640
DO - 10.1109/VLSIT.2018.8510640
M3 - Conference contribution
AN - SCOPUS:85056824229
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - 139
EP - 140
BT - 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018
Y2 - 18 June 2018 through 22 June 2018
ER -