Achieving high-scalability negative capacitance FETs with uniform Sub-35 mV/dec switch using dopant-free hafnium oxide and gate strain

Chia Chi Fan, Chun Hu Cheng, Chun Yuan Tu, Chien Liu, Wan Hsin Chen, Tun Jen Chang, Chun Yen Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

For the first time, we successfully demonstrated that the 4-nm-thick dopant-free HfO2 NCFETs using gate strain can implement an energy-efficient switch of a low gate overdrive voltage and a nearly hysteresis-free sub-40 mV/dec swing. The gate strain favorably rearranges oxygen vacancies and boosts orthorhombic phase transition. Furthermore, the dopant-free HfO2 NCFET can be further improved by in-situ nitridation process. The 4-nm-thick nitrided HfO2 NCFETs achieve a steep symmetric sub-35 mV/dec switch, a sustained sub-40 mV/dec SS distribution, and excellent stress immunity during NC switch. The high-scalability and dopant-free NCFET shows the great potential for the application of future highly-scaled 3D CMOS technology.

Original languageEnglish
Title of host publication2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages139-140
Number of pages2
ISBN (Electronic)9781538642160
DOIs
Publication statusPublished - 2018 Oct 25
Event38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 - Honolulu, United States
Duration: 2018 Jun 182018 Jun 22

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2018-June
ISSN (Print)0743-1562

Other

Other38th IEEE Symposium on VLSI Technology, VLSI Technology 2018
CountryUnited States
CityHonolulu
Period18/6/1818/6/22

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Fan, C. C., Cheng, C. H., Tu, C. Y., Liu, C., Chen, W. H., Chang, T. J., & Chang, C. Y. (2018). Achieving high-scalability negative capacitance FETs with uniform Sub-35 mV/dec switch using dopant-free hafnium oxide and gate strain. In 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018 (pp. 139-140). [8510640] (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2018-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2018.8510640