A World First QLC RRAM: Highly Reliable Resistive-Gate Flash with Record 108Endurance and Excellent Retention

M. Y. Li; J. P. Lee; C. H. Liu; J. C. Guo; Steve S. Chung

doi:10.1109/IRPS48203.2023.10117748

A World First QLC RRAM: Highly Reliable Resistive-Gate Flash with Record 10⁸Endurance and Excellent Retention

M. Y. Li, J. P. Lee, C. H. Liu, J. C. Guo, Steve S. Chung^*

^*Corresponding author for this work

Department of Mechatronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, we demonstrated successfully a quad-level cell (QLC) of a resistive-gate memory. It was implemented in a 1k bits chip with integration of FinFET core on a mature logic platform. Comprehensive reliabilities have been examined. The results show the forming-free property, low programming current (< μ A), high endurance and excellent data retention. A record high 5×108 endurance can be achieved. Furthermore, a 4-bit-per-cell (16 levels) has been demonstrated successfully. The chip-level performance is also analyzed, showing well disturbance-immune during SET/RESET, READ, which kept healthy signal-to-noise margin, 2-3x. This architecture is a strong candidate for the next generation resistance memory.

Original language	English
Title of host publication	2023 IEEE International Reliability Physics Symposium, IRPS 2023 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781665456722
DOIs	https://doi.org/10.1109/IRPS48203.2023.10117748
Publication status	Published - 2023
Event	61st IEEE International Reliability Physics Symposium, IRPS 2023 - Monterey, United States Duration: 2023 Mar 26 → 2023 Mar 30

Publication series

Name	IEEE International Reliability Physics Symposium Proceedings
Volume	2023-March
ISSN (Print)	1541-7026

Conference

Conference	61st IEEE International Reliability Physics Symposium, IRPS 2023
Country/Territory	United States
City	Monterey
Period	2023/03/26 → 2023/03/30

Keywords

FinFET
Quad-level Cell (QLC)
RG-Flash
RRAM
Reliability
Resistance memory

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1109/IRPS48203.2023.10117748

Cite this

Li, M. Y., Lee, J. P., Liu, C. H., Guo, J. C., & Chung, S. S. (2023). A World First QLC RRAM: Highly Reliable Resistive-Gate Flash with Record 10⁸Endurance and Excellent Retention. In 2023 IEEE International Reliability Physics Symposium, IRPS 2023 - Proceedings (IEEE International Reliability Physics Symposium Proceedings; Vol. 2023-March). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IRPS48203.2023.10117748

A World First QLC RRAM: Highly Reliable Resistive-Gate Flash with Record 10⁸Endurance and Excellent Retention. / Li, M. Y.; Lee, J. P.; Liu, C. H. et al.
2023 IEEE International Reliability Physics Symposium, IRPS 2023 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2023. (IEEE International Reliability Physics Symposium Proceedings; Vol. 2023-March).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Li, MY, Lee, JP, Liu, CH, Guo, JC & Chung, SS 2023, A World First QLC RRAM: Highly Reliable Resistive-Gate Flash with Record 10⁸Endurance and Excellent Retention. in 2023 IEEE International Reliability Physics Symposium, IRPS 2023 - Proceedings. IEEE International Reliability Physics Symposium Proceedings, vol. 2023-March, Institute of Electrical and Electronics Engineers Inc., 61st IEEE International Reliability Physics Symposium, IRPS 2023, Monterey, United States, 2023/03/26. https://doi.org/10.1109/IRPS48203.2023.10117748

Li MY, Lee JP, Liu CH, Guo JC, Chung SS. A World First QLC RRAM: Highly Reliable Resistive-Gate Flash with Record 10⁸Endurance and Excellent Retention. In 2023 IEEE International Reliability Physics Symposium, IRPS 2023 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2023. (IEEE International Reliability Physics Symposium Proceedings). doi: 10.1109/IRPS48203.2023.10117748

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abstract = "In this paper, we demonstrated successfully a quad-level cell (QLC) of a resistive-gate memory. It was implemented in a 1k bits chip with integration of FinFET core on a mature logic platform. Comprehensive reliabilities have been examined. The results show the forming-free property, low programming current (< μ A), high endurance and excellent data retention. A record high 5×108 endurance can be achieved. Furthermore, a 4-bit-per-cell (16 levels) has been demonstrated successfully. The chip-level performance is also analyzed, showing well disturbance-immune during SET/RESET, READ, which kept healthy signal-to-noise margin, 2-3x. This architecture is a strong candidate for the next generation resistance memory.",

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note = "Funding Information: *This work was supported by the Ministry of Science and Technology, Taiwan, under MOST 108-2221-E-009-015-MY3, and MOST111-2218-E-A49-018-MBK. Publisher Copyright: {\textcopyright} 2023 IEEE.; 61st IEEE International Reliability Physics Symposium, IRPS 2023 ; Conference date: 26-03-2023 Through 30-03-2023",

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N2 - In this paper, we demonstrated successfully a quad-level cell (QLC) of a resistive-gate memory. It was implemented in a 1k bits chip with integration of FinFET core on a mature logic platform. Comprehensive reliabilities have been examined. The results show the forming-free property, low programming current (< μ A), high endurance and excellent data retention. A record high 5×108 endurance can be achieved. Furthermore, a 4-bit-per-cell (16 levels) has been demonstrated successfully. The chip-level performance is also analyzed, showing well disturbance-immune during SET/RESET, READ, which kept healthy signal-to-noise margin, 2-3x. This architecture is a strong candidate for the next generation resistance memory.

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