TY - GEN
T1 - A simulation study on dispatching rules in semiconductor wafer fabrication facilities with due date-based objectives
AU - Chiang, Tsung Che
AU - Fu, Li Chen
PY - 2006
Y1 - 2006
N2 - This paper addresses the lot scheduling problem in the semiconductor wafer fabrication facilities. We provide a simulation study to examine the performance of sixteen existing dispatching rules on the tardy rate, mean tardiness, and the maximum tardiness. A public and representative test bed, the MIMAC (Measurement and Improvement of MAnufacturing Capacities) test bed is used. The best rules with respect to each objective are identified through the experiments, and some Undings are provided to be guidelines for designing new dispatching rules.
AB - This paper addresses the lot scheduling problem in the semiconductor wafer fabrication facilities. We provide a simulation study to examine the performance of sixteen existing dispatching rules on the tardy rate, mean tardiness, and the maximum tardiness. A public and representative test bed, the MIMAC (Measurement and Improvement of MAnufacturing Capacities) test bed is used. The best rules with respect to each objective are identified through the experiments, and some Undings are provided to be guidelines for designing new dispatching rules.
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U2 - 10.1109/ICSMC.2006.385039
DO - 10.1109/ICSMC.2006.385039
M3 - Conference contribution
AN - SCOPUS:34548133758
SN - 1424401003
SN - 9781424401000
T3 - Conference Proceedings - IEEE International Conference on Systems, Man and Cybernetics
SP - 4660
EP - 4665
BT - 2006 IEEE International Conference on Systems, Man and Cybernetics
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2006 IEEE International Conference on Systems, Man and Cybernetics
Y2 - 8 October 2006 through 11 October 2006
ER -