A simulation study on dispatching rules in semiconductor wafer fabrication facilities with due date-based objectives

Tsung Che Chiang, Li Chen Fu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

This paper addresses the lot scheduling problem in the semiconductor wafer fabrication facilities. We provide a simulation study to examine the performance of sixteen existing dispatching rules on the tardy rate, mean tardiness, and the maximum tardiness. A public and representative test bed, the MIMAC (Measurement and Improvement of MAnufacturing Capacities) test bed is used. The best rules with respect to each objective are identified through the experiments, and some Undings are provided to be guidelines for designing new dispatching rules.

Original languageEnglish
Title of host publication2006 IEEE International Conference on Systems, Man and Cybernetics
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages4660-4665
Number of pages6
ISBN (Print)1424401003, 9781424401000
DOIs
Publication statusPublished - 2006 Jan 1
Event2006 IEEE International Conference on Systems, Man and Cybernetics - Taipei, Taiwan
Duration: 2006 Oct 82006 Oct 11

Publication series

NameConference Proceedings - IEEE International Conference on Systems, Man and Cybernetics
Volume6
ISSN (Print)1062-922X

Other

Other2006 IEEE International Conference on Systems, Man and Cybernetics
CountryTaiwan
CityTaipei
Period06/10/806/10/11

ASJC Scopus subject areas

  • Engineering(all)

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    Chiang, T. C., & Fu, L. C. (2006). A simulation study on dispatching rules in semiconductor wafer fabrication facilities with due date-based objectives. In 2006 IEEE International Conference on Systems, Man and Cybernetics (pp. 4660-4665). [4274648] (Conference Proceedings - IEEE International Conference on Systems, Man and Cybernetics; Vol. 6). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICSMC.2006.385039