A quadruple-sampling second-order delta-sigma modulator

Chien Hung Kuo; Wei Wei Tseng

doi:10.1109/GCCE.2016.7800473

A quadruple-sampling second-order delta-sigma modulator

Chien Hung Kuo, Wei Wei Tseng

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, a 1.8-V 3-bit quadruple-sampling delta-sigma modulator for audio application is presented. To performance high-resolution and low-cost modulator, a single opamp is used to complete the integration with four phases. Since the phase difference between any two succeeding clocks is 90 degrees, the sampling rate will be four times of clock frequency. The effective integration time can also be increased, and thus relaxing the requirements of opamp. From the simulation results, the proposed modulator achieves a peak SNDR of 104.5 dB for 20-kHz signal bandwidth under 1.8-V supply voltage and 2.56 MHz clock rate.

Original language	English
Title of host publication	2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509023332
DOIs	https://doi.org/10.1109/GCCE.2016.7800473
Publication status	Published - 2016 Dec 27
Event	5th IEEE Global Conference on Consumer Electronics, GCCE 2016 - Kyoto, Japan Duration: 2016 Oct 11 → 2016 Oct 14

Publication series

Name	2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016

Other

Other	5th IEEE Global Conference on Consumer Electronics, GCCE 2016
Country/Territory	Japan
City	Kyoto
Period	2016/10/11 → 2016/10/14

Keywords

Multibit DSM
Quadruple-Sampling
Time-Interleaved

ASJC Scopus subject areas

Signal Processing
Electrical and Electronic Engineering
Computer Science Applications
Hardware and Architecture
Instrumentation

Access to Document

10.1109/GCCE.2016.7800473

Cite this

A quadruple-sampling second-order delta-sigma modulator. / Kuo, Chien Hung; Tseng, Wei Wei.
2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7800473 (2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kuo, CH & Tseng, WW 2016, A quadruple-sampling second-order delta-sigma modulator. in 2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016., 7800473, 2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016, Institute of Electrical and Electronics Engineers Inc., 5th IEEE Global Conference on Consumer Electronics, GCCE 2016, Kyoto, Japan, 2016/10/11. https://doi.org/10.1109/GCCE.2016.7800473

@inproceedings{ee29dbf36f7b44eb891b78d42c70c502,

title = "A quadruple-sampling second-order delta-sigma modulator",

abstract = "In this paper, a 1.8-V 3-bit quadruple-sampling delta-sigma modulator for audio application is presented. To performance high-resolution and low-cost modulator, a single opamp is used to complete the integration with four phases. Since the phase difference between any two succeeding clocks is 90 degrees, the sampling rate will be four times of clock frequency. The effective integration time can also be increased, and thus relaxing the requirements of opamp. From the simulation results, the proposed modulator achieves a peak SNDR of 104.5 dB for 20-kHz signal bandwidth under 1.8-V supply voltage and 2.56 MHz clock rate.",

keywords = "Multibit DSM, Quadruple-Sampling, Time-Interleaved",

author = "Kuo, {Chien Hung} and Tseng, {Wei Wei}",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 5th IEEE Global Conference on Consumer Electronics, GCCE 2016 ; Conference date: 11-10-2016 Through 14-10-2016",

year = "2016",

month = dec,

day = "27",

doi = "10.1109/GCCE.2016.7800473",

language = "English",

series = "2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016",

}

TY - GEN

T1 - A quadruple-sampling second-order delta-sigma modulator

AU - Kuo, Chien Hung

AU - Tseng, Wei Wei

PY - 2016/12/27

Y1 - 2016/12/27

N2 - In this paper, a 1.8-V 3-bit quadruple-sampling delta-sigma modulator for audio application is presented. To performance high-resolution and low-cost modulator, a single opamp is used to complete the integration with four phases. Since the phase difference between any two succeeding clocks is 90 degrees, the sampling rate will be four times of clock frequency. The effective integration time can also be increased, and thus relaxing the requirements of opamp. From the simulation results, the proposed modulator achieves a peak SNDR of 104.5 dB for 20-kHz signal bandwidth under 1.8-V supply voltage and 2.56 MHz clock rate.

AB - In this paper, a 1.8-V 3-bit quadruple-sampling delta-sigma modulator for audio application is presented. To performance high-resolution and low-cost modulator, a single opamp is used to complete the integration with four phases. Since the phase difference between any two succeeding clocks is 90 degrees, the sampling rate will be four times of clock frequency. The effective integration time can also be increased, and thus relaxing the requirements of opamp. From the simulation results, the proposed modulator achieves a peak SNDR of 104.5 dB for 20-kHz signal bandwidth under 1.8-V supply voltage and 2.56 MHz clock rate.

KW - Multibit DSM

KW - Quadruple-Sampling

KW - Time-Interleaved

UR - http://www.scopus.com/inward/record.url?scp=85010417494&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85010417494&partnerID=8YFLogxK

U2 - 10.1109/GCCE.2016.7800473

DO - 10.1109/GCCE.2016.7800473

M3 - Conference contribution

AN - SCOPUS:85010417494

T3 - 2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016

BT - 2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 5th IEEE Global Conference on Consumer Electronics, GCCE 2016

Y2 - 11 October 2016 through 14 October 2016

ER -

A quadruple-sampling second-order delta-sigma modulator

Abstract

Publication series

Other

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this