A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications

E. R. Hsieh; Y. C. Fan; K. Y. Chang; C. H. Liu; C. H. Chien; Steve S. Chung

doi:10.1109/VLSI-TSA.2017.7942487

A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications

E. R. Hsieh, Y. C. Fan, K. Y. Chang, C. H. Liu, C. H. Chien, Steve S. Chung

Department of Mechatronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

A novel complementary tunneling FET (C-TFET) has been designed and targeted for the low power and appropriate performance applications (Apps). In this new architecture of C-TFET, the drain and source (D/S) are configured as a staggered structure to increase the tunneling current, and the conventional p-i-n junction C-TFET has been modified as a p-n junction to further enhance the I_on current. The results show that new design can achieve 310uA/um(n), 440uA/um(p) TFETs of I_on, comparable to those of LP planar CMOS devices, 0.1 nA/um of I_off, while excellent S.S.(<10mV/dec) at Vdd= 0.7V, which will be a promising candidate for the low-power and appropriate performance apps in the next decade.

Original language	English
Title of host publication	2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509058051
DOIs	https://doi.org/10.1109/VLSI-TSA.2017.7942487
Publication status	Published - 2017 Jun 7
Event	2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017 - Hsinchu, Taiwan Duration: 2017 Apr 24 → 2017 Apr 27

Publication series

Name	2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017

Other

Other	2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017
Country/Territory	Taiwan
City	Hsinchu
Period	2017/04/24 → 2017/04/27

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/VLSI-TSA.2017.7942487

Cite this

Hsieh, E. R., Fan, Y. C., Chang, K. Y., Liu, C. H., Chien, C. H., & Chung, S. S. (2017). A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications. In 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017 Article 7942487 (2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-TSA.2017.7942487

A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications. / Hsieh, E. R.; Fan, Y. C.; Chang, K. Y. et al.
2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017. Institute of Electrical and Electronics Engineers Inc., 2017. 7942487 (2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hsieh, ER, Fan, YC, Chang, KY, Liu, CH, Chien, CH & Chung, SS 2017, A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications. in 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017., 7942487, 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017, Institute of Electrical and Electronics Engineers Inc., 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017, Hsinchu, Taiwan, 2017/04/24. https://doi.org/10.1109/VLSI-TSA.2017.7942487

Hsieh ER, Fan YC, Chang KY, Liu CH, Chien CH, Chung SS. A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications. In 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017. Institute of Electrical and Electronics Engineers Inc. 2017. 7942487. (2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017). doi: 10.1109/VLSI-TSA.2017.7942487

Hsieh, E. R. ; Fan, Y. C. ; Chang, K. Y. et al. / A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications. 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017. Institute of Electrical and Electronics Engineers Inc., 2017. (2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017).

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title = "A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications",

abstract = "A novel complementary tunneling FET (C-TFET) has been designed and targeted for the low power and appropriate performance applications (Apps). In this new architecture of C-TFET, the drain and source (D/S) are configured as a staggered structure to increase the tunneling current, and the conventional p-i-n junction C-TFET has been modified as a p-n junction to further enhance the Ion current. The results show that new design can achieve 310uA/um(n), 440uA/um(p) TFETs of Ion, comparable to those of LP planar CMOS devices, 0.1 nA/um of Ioff, while excellent S.S.(<10mV/dec) at Vdd= 0.7V, which will be a promising candidate for the low-power and appropriate performance apps in the next decade.",

author = "Hsieh, {E. R.} and Fan, {Y. C.} and Chang, {K. Y.} and Liu, {C. H.} and Chien, {C. H.} and Chung, {Steve S.}",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017 ; Conference date: 24-04-2017 Through 27-04-2017",

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AU - Liu, C. H.

AU - Chien, C. H.

AU - Chung, Steve S.

PY - 2017/6/7

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N2 - A novel complementary tunneling FET (C-TFET) has been designed and targeted for the low power and appropriate performance applications (Apps). In this new architecture of C-TFET, the drain and source (D/S) are configured as a staggered structure to increase the tunneling current, and the conventional p-i-n junction C-TFET has been modified as a p-n junction to further enhance the Ion current. The results show that new design can achieve 310uA/um(n), 440uA/um(p) TFETs of Ion, comparable to those of LP planar CMOS devices, 0.1 nA/um of Ioff, while excellent S.S.(<10mV/dec) at Vdd= 0.7V, which will be a promising candidate for the low-power and appropriate performance apps in the next decade.

AB - A novel complementary tunneling FET (C-TFET) has been designed and targeted for the low power and appropriate performance applications (Apps). In this new architecture of C-TFET, the drain and source (D/S) are configured as a staggered structure to increase the tunneling current, and the conventional p-i-n junction C-TFET has been modified as a p-n junction to further enhance the Ion current. The results show that new design can achieve 310uA/um(n), 440uA/um(p) TFETs of Ion, comparable to those of LP planar CMOS devices, 0.1 nA/um of Ioff, while excellent S.S.(<10mV/dec) at Vdd= 0.7V, which will be a promising candidate for the low-power and appropriate performance apps in the next decade.

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A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications

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