A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications

E. R. Hsieh, Y. C. Fan, K. Y. Chang, C. H. Liu, C. H. Chien, Steve S. Chung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A novel complementary tunneling FET (C-TFET) has been designed and targeted for the low power and appropriate performance applications (Apps). In this new architecture of C-TFET, the drain and source (D/S) are configured as a staggered structure to increase the tunneling current, and the conventional p-i-n junction C-TFET has been modified as a p-n junction to further enhance the Ion current. The results show that new design can achieve 310uA/um(n), 440uA/um(p) TFETs of Ion, comparable to those of LP planar CMOS devices, 0.1 nA/um of Ioff, while excellent S.S.(<10mV/dec) at Vdd= 0.7V, which will be a promising candidate for the low-power and appropriate performance apps in the next decade.

Original languageEnglish
Title of host publication2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509058051
DOIs
Publication statusPublished - 2017 Jun 7
Event2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017 - Hsinchu, Taiwan
Duration: 2017 Apr 242017 Apr 27

Publication series

Name2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017

Other

Other2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017
CountryTaiwan
CityHsinchu
Period2017/04/242017/04/27

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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