TY - JOUR
T1 - A multi-band fast-locking delay-locked loop with jitter-bounded feature
AU - Kuo, Chien Hung
AU - Lai, Hung Jing
AU - Lin, Meng Feng
N1 - Funding Information:
Manuscript received July 22, 2010; accepted september 29, 2010. This research was supported in part by a grant of making chips from national chip Implementation center (cIc). The authors also would like to thank national science council of Taiwan for the financial support of this project. c.-H. Kuo and H.-J. lai are with national Taiwan normal University, applied Electronics Technology, Taipei, Taiwan (e-mail: chk@ ntnu.edu.tw).
PY - 2011/1
Y1 - 2011/1
N2 - In this paper, a fast-locking delay-locked loop (DLL) with jitter-bounded feature is presented. In the proposed fast-locking mechanism, a frequency estimator and a programmable voltage circuit are developed to rapidly switch the control node of voltage-controlled delay line to a voltage level near the final required value. After that, the DLL output will be quickly locked by the following charge pumping on the loop filter. In the jitter-bounded approach, two phase-frequency detectors and a tunable delay are employed to hold the output clock jitter between two reference inputs after the DLL is locked. Furthermore, to enhance the flexibility of the presented DLL, a frequency multiplier with fewer active devices is also developed to provide high-frequency clock output for wideband applications. The presented DLL is implemented in a 0.18-m 1P6M CMOS technology. The active area without contact pads is 0.34 × 0.41 mm2. A minimum lock time of six clock cycles is measured from no reference input to locked state. The output frequency ranges of the DLL and the frequency multiplier can be measured from 200 to 400 MHz and from 1 to 2 GHz, respectively. The power dissipation of the presented DLL is 31.5 mW at a 1.8 V supply voltage.
AB - In this paper, a fast-locking delay-locked loop (DLL) with jitter-bounded feature is presented. In the proposed fast-locking mechanism, a frequency estimator and a programmable voltage circuit are developed to rapidly switch the control node of voltage-controlled delay line to a voltage level near the final required value. After that, the DLL output will be quickly locked by the following charge pumping on the loop filter. In the jitter-bounded approach, two phase-frequency detectors and a tunable delay are employed to hold the output clock jitter between two reference inputs after the DLL is locked. Furthermore, to enhance the flexibility of the presented DLL, a frequency multiplier with fewer active devices is also developed to provide high-frequency clock output for wideband applications. The presented DLL is implemented in a 0.18-m 1P6M CMOS technology. The active area without contact pads is 0.34 × 0.41 mm2. A minimum lock time of six clock cycles is measured from no reference input to locked state. The output frequency ranges of the DLL and the frequency multiplier can be measured from 200 to 400 MHz and from 1 to 2 GHz, respectively. The power dissipation of the presented DLL is 31.5 mW at a 1.8 V supply voltage.
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U2 - 10.1109/TUFFC.2011.1773
DO - 10.1109/TUFFC.2011.1773
M3 - Article
AN - SCOPUS:78751660689
SN - 0885-3010
VL - 58
SP - 51
EP - 59
JO - IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control
JF - IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control
IS - 1
M1 - 5688400
ER -