TY - JOUR
T1 - A low-voltage fourth-order cascade delta - Sigma modulator in 0.18-μm CMOS
AU - Kuo, Chien Hung
AU - Shi, Deng Yao
AU - Chang, Kang Shuo
N1 - Funding Information:
Manuscript received October 13, 2009; revised January 17, 2010; accepted February 19, 2010. Date of publication April 29, 2010; date of current version October 01, 2010. This work was supported in part by the National Science Council, Taiwan, under Grant NSC 98-2220-E-003-004 and in part by a grant of making chips from the National Chip Implementation Center (CIC). This paper was recommended by Associate Editor G. Manganaro.
PY - 2010
Y1 - 2010
N2 - In this paper, a low-voltage fourth-order 2-2 cascade delta - Sigma Δ Σ modulator using the proposed double-sampling switched-operational- amplifier (SOP)-based integrator is presented. In the analog part of the Δ Σ modulator, most of the power consumption comes from the SOP used in the integrator. Hence, the requirement of the SOP must effectively be relaxed to reduce the power consumption of the modulator. In each cascade stage, the second-order Δ Σ modulator with a cascade-of-integrators input feedforward structure is used to reduce the output swing. The second integrator output of the first stage is directly connected to the second stage to simplify circuit design on the analog part. Furthermore, the double-sampling SOP-based integrator is also adopted to reduce the applied clock frequency by half. In this paper, systematic means of designing the presented modulator and searching the minimum current of the SOP in a specified supply voltage are also developed. The presented Δ Σ modulator is fabricated in a 0.18- μ 1P6M CMOS technology. The chip core area without PADs is 1.57mm2. The modulator achieves an 84-dB peak signal-to-noise plus distortion ratio and an 88-dB dynamic range in 20-kHz signal bandwidth with a clock frequency of 2 MHz. The power consumption of the presented modulator core is 0.66 mW at a supply voltage of 1 V. The presented modulator can also be operated in a wide range of supply voltages from 1.8 V down to 0.9 V without seriously degrading the performance.
AB - In this paper, a low-voltage fourth-order 2-2 cascade delta - Sigma Δ Σ modulator using the proposed double-sampling switched-operational- amplifier (SOP)-based integrator is presented. In the analog part of the Δ Σ modulator, most of the power consumption comes from the SOP used in the integrator. Hence, the requirement of the SOP must effectively be relaxed to reduce the power consumption of the modulator. In each cascade stage, the second-order Δ Σ modulator with a cascade-of-integrators input feedforward structure is used to reduce the output swing. The second integrator output of the first stage is directly connected to the second stage to simplify circuit design on the analog part. Furthermore, the double-sampling SOP-based integrator is also adopted to reduce the applied clock frequency by half. In this paper, systematic means of designing the presented modulator and searching the minimum current of the SOP in a specified supply voltage are also developed. The presented Δ Σ modulator is fabricated in a 0.18- μ 1P6M CMOS technology. The chip core area without PADs is 1.57mm2. The modulator achieves an 84-dB peak signal-to-noise plus distortion ratio and an 88-dB dynamic range in 20-kHz signal bandwidth with a clock frequency of 2 MHz. The power consumption of the presented modulator core is 0.66 mW at a supply voltage of 1 V. The presented modulator can also be operated in a wide range of supply voltages from 1.8 V down to 0.9 V without seriously degrading the performance.
KW - Analog-to-digital converter
KW - deltasigma modulator
KW - double sampling
KW - low voltage
KW - switched operational amplifier (SOP)
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U2 - 10.1109/TCSI.2010.2046231
DO - 10.1109/TCSI.2010.2046231
M3 - Article
AN - SCOPUS:77957753939
SN - 1549-8328
VL - 57
SP - 2450
EP - 2461
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 9
M1 - 5456228
ER -