A low-power 24 GHz phase lock loop with gain-boosted charge pump embedded in 0.18 μm COMS technology

Min Huang; Chia Hui Yu; Jeng Han Tsai; Tian Wei Huang

doi:10.1109/APMC.2012.6421689

A low-power 24 GHz phase lock loop with gain-boosted charge pump embedded in 0.18 μm COMS technology

Min Huang^*, Chia Hui Yu, Jeng Han Tsai, Tian Wei Huang

^*Corresponding author for this work

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

A 24 GHz PLL using 0.18-μm CMOS technology is presented in this paper. To achieve the low-power consumption and low phase-noise performance, a transformerfeedback voltage control oscillator (TF-VCO) and a cascoded frequency divider including injection-locked frequency divider (ILFD) and current mode logic divider (CML) are implemented. Further- more, the gain-boosted technique was adopted in charge pump to reduce current mismatch. The phase noise of proposed PLL is measured by -83.79 dBc/Hz at 1 MHz offset and -123.61 dBc/Hz at 10 MHz offset. The power consumption is 29.8 mW (only 13.3 mW in VCO and ILFD).

Original language	English
Title of host publication	2012 Asia-Pacific Microwave Conference, APMC 2012 - Proceedings
Pages	643-645
Number of pages	3
DOIs	https://doi.org/10.1109/APMC.2012.6421689
Publication status	Published - 2012
Event	2012 Asia-Pacific Microwave Conference, APMC 2012 - Kaohsiung, Taiwan Duration: 2012 Dec 4 → 2012 Dec 7

Publication series

Name	Asia-Pacific Microwave Conference Proceedings, APMC

Other

Other	2012 Asia-Pacific Microwave Conference, APMC 2012
Country/Territory	Taiwan
City	Kaohsiung
Period	2012/12/04 → 2012/12/07

Keywords

Phase-lock-loop
gain-boosted
injection-locked frequency divider
transformer-feedback
voltage control oscillator

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/APMC.2012.6421689

Cite this

A low-power 24 GHz phase lock loop with gain-boosted charge pump embedded in 0.18 μm COMS technology. / Huang, Min; Yu, Chia Hui; Tsai, Jeng Han et al.
2012 Asia-Pacific Microwave Conference, APMC 2012 - Proceedings. 2012. p. 643-645 6421689 (Asia-Pacific Microwave Conference Proceedings, APMC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Huang, M, Yu, CH, Tsai, JH & Huang, TW 2012, A low-power 24 GHz phase lock loop with gain-boosted charge pump embedded in 0.18 μm COMS technology. in 2012 Asia-Pacific Microwave Conference, APMC 2012 - Proceedings., 6421689, Asia-Pacific Microwave Conference Proceedings, APMC, pp. 643-645, 2012 Asia-Pacific Microwave Conference, APMC 2012, Kaohsiung, Taiwan, 2012/12/04. https://doi.org/10.1109/APMC.2012.6421689

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title = "A low-power 24 GHz phase lock loop with gain-boosted charge pump embedded in 0.18 μm COMS technology",

abstract = "A 24 GHz PLL using 0.18-μm CMOS technology is presented in this paper. To achieve the low-power consumption and low phase-noise performance, a transformerfeedback voltage control oscillator (TF-VCO) and a cascoded frequency divider including injection-locked frequency divider (ILFD) and current mode logic divider (CML) are implemented. Further- more, the gain-boosted technique was adopted in charge pump to reduce current mismatch. The phase noise of proposed PLL is measured by -83.79 dBc/Hz at 1 MHz offset and -123.61 dBc/Hz at 10 MHz offset. The power consumption is 29.8 mW (only 13.3 mW in VCO and ILFD).",

keywords = "Phase-lock-loop, gain-boosted, injection-locked frequency divider, transformer-feedback, voltage control oscillator",

author = "Min Huang and Yu, {Chia Hui} and Tsai, {Jeng Han} and Huang, {Tian Wei}",

year = "2012",

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AU - Huang, Min

AU - Yu, Chia Hui

AU - Tsai, Jeng Han

AU - Huang, Tian Wei

PY - 2012

Y1 - 2012

N2 - A 24 GHz PLL using 0.18-μm CMOS technology is presented in this paper. To achieve the low-power consumption and low phase-noise performance, a transformerfeedback voltage control oscillator (TF-VCO) and a cascoded frequency divider including injection-locked frequency divider (ILFD) and current mode logic divider (CML) are implemented. Further- more, the gain-boosted technique was adopted in charge pump to reduce current mismatch. The phase noise of proposed PLL is measured by -83.79 dBc/Hz at 1 MHz offset and -123.61 dBc/Hz at 10 MHz offset. The power consumption is 29.8 mW (only 13.3 mW in VCO and ILFD).

AB - A 24 GHz PLL using 0.18-μm CMOS technology is presented in this paper. To achieve the low-power consumption and low phase-noise performance, a transformerfeedback voltage control oscillator (TF-VCO) and a cascoded frequency divider including injection-locked frequency divider (ILFD) and current mode logic divider (CML) are implemented. Further- more, the gain-boosted technique was adopted in charge pump to reduce current mismatch. The phase noise of proposed PLL is measured by -83.79 dBc/Hz at 1 MHz offset and -123.61 dBc/Hz at 10 MHz offset. The power consumption is 29.8 mW (only 13.3 mW in VCO and ILFD).

KW - Phase-lock-loop

KW - gain-boosted

KW - injection-locked frequency divider

KW - transformer-feedback

KW - voltage control oscillator

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A low-power 24 GHz phase lock loop with gain-boosted charge pump embedded in 0.18 μm COMS technology

Abstract

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Keywords

ASJC Scopus subject areas

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