A low-power 24 GHz phase lock loop with gain-boosted charge pump embedded in 0.18 μm COMS technology

Min Huang, Chia Hui Yu, Jeng Han Tsai, Tian Wei Huang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A 24 GHz PLL using 0.18-μm CMOS technology is presented in this paper. To achieve the low-power consumption and low phase-noise performance, a transformerfeedback voltage control oscillator (TF-VCO) and a cascoded frequency divider including injection-locked frequency divider (ILFD) and current mode logic divider (CML) are implemented. Further- more, the gain-boosted technique was adopted in charge pump to reduce current mismatch. The phase noise of proposed PLL is measured by -83.79 dBc/Hz at 1 MHz offset and -123.61 dBc/Hz at 10 MHz offset. The power consumption is 29.8 mW (only 13.3 mW in VCO and ILFD).

Original languageEnglish
Title of host publication2012 Asia-Pacific Microwave Conference, APMC 2012 - Proceedings
Pages643-645
Number of pages3
DOIs
Publication statusPublished - 2012 Dec 1
Event2012 Asia-Pacific Microwave Conference, APMC 2012 - Kaohsiung, Taiwan
Duration: 2012 Dec 42012 Dec 7

Publication series

NameAsia-Pacific Microwave Conference Proceedings, APMC

Other

Other2012 Asia-Pacific Microwave Conference, APMC 2012
CountryTaiwan
CityKaohsiung
Period12/12/412/12/7

Keywords

  • Phase-lock-loop
  • gain-boosted
  • injection-locked frequency divider
  • transformer-feedback
  • voltage control oscillator

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Huang, M., Yu, C. H., Tsai, J. H., & Huang, T. W. (2012). A low-power 24 GHz phase lock loop with gain-boosted charge pump embedded in 0.18 μm COMS technology. In 2012 Asia-Pacific Microwave Conference, APMC 2012 - Proceedings (pp. 643-645). [6421689] (Asia-Pacific Microwave Conference Proceedings, APMC). https://doi.org/10.1109/APMC.2012.6421689