A K-Band 42.7% PAE Power Amplifier Supporting Two Carrier Aggregation in 90 nm CMOS

This paper presents the design and evaluation of a high-efficiency Power Amplifier (PA) fabricated using 90 nm CMOS technology. The PA employs a one-stage differential common source (CS) Class-F topology optimized for nextgeneration wireless communications and satellite applications. Key design features include a unique harmonic control circuit within the output matching network and the use of neutralization techniques to enhance stability and gain. The PA demonstrates excellent power-added efficiency (PAE) across the bandwidth of 17.2 to 20.2 GHz, achieving a peak PAE of over 42.7%. The PA achieves output power (P_o) of 8 dBm when error vector magnitude (EVM) < -25 dBm by 2 component carriers (2CC) for 64-QAM signals at 18 GHz. This work highlights significant advancements in PA design by attaining high efficiency and robust performance using a relatively simple and cost-effective CMOS process.