A highly scalable poly-Si junctionless FETs featuring a novel multi-stacking hybrid P/N layer and vertical gate with very high Ion/Ioff for 3D stacked ICs

Ya Chi Cheng, Hung Bin Chen, Chun Yen Chang, Chun Hu Cheng, Yi Jia Shih, Yung Chun Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

This work demonstrates for the first time a three-dimensional (3D) stacked hybrid P/N layer for p-channel junctionless thin-film transistor (JL-TFT) with nanowire (NW) structures. Relative to conventional stacked devices, the 3D stacked hybrid P/N JL-TFT exhibits a high Ion/Ioff current ratio (>109), a steep subthreshold swing (SS) of 70 mV/dec, a low drain-induced barrier lowering (DIBL) value of 3.5 mV/V; these properties are achieved by reducing the effective channel thickness that is determined by the channel/substrate junction. The developed stacked hybrid P/N exhibits reduced low-frequency noise, less sensitive temperature coefficients and performance variation in both threshold voltage (Vth) and SS, and so is suit for high-density 3D stacked integrated circuit (IC) applications.

Original languageEnglish
Title of host publication2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509006373
DOIs
Publication statusPublished - 2016 Sep 21
Event36th IEEE Symposium on VLSI Technology, VLSI Technology 2016 - Honolulu, United States
Duration: 2016 Jun 132016 Jun 16

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2016-September
ISSN (Print)0743-1562

Other

Other36th IEEE Symposium on VLSI Technology, VLSI Technology 2016
CountryUnited States
CityHonolulu
Period16/6/1316/6/16

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Cheng, Y. C., Chen, H. B., Chang, C. Y., Cheng, C. H., Shih, Y. J., & Wu, Y. C. (2016). A highly scalable poly-Si junctionless FETs featuring a novel multi-stacking hybrid P/N layer and vertical gate with very high Ion/Ioff for 3D stacked ICs. In 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016 [7573429] (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2016-September). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2016.7573429