A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant

Kuan Yu Lin; Ming Dou Ker; Chun Yu Lin

doi:10.1109/ISCAS.2014.6865109

A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant

Kuan Yu Lin, Ming Dou Ker, Chun Yu Lin

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

A biomedical stimulator with four high-voltagetolerant output channels, combined with on-chip positive high voltage generator, is proposed. For the purpose of integration with other circuit blocks into a system-on-chip (SoC) for cochlear implant biomedical applications, this design has been realized with the 1.8-V/3.3-V transistors in a 0.18-μm CMOS process. This stimulator only needs one single supply voltage of 1.8 V, but the maximum stimulation voltage can be as high as 7 V. The dynamic bias technique and stacked MOS configuration are used to implement this stimulator in the low-voltage CMOS process, without causing the issues of electrical overstress and gate-oxide reliability during circuit operation.

Original language	English
Title of host publication	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	237-240
Number of pages	4
ISBN (Print)	9781479934324
DOIs	https://doi.org/10.1109/ISCAS.2014.6865109
Publication status	Published - 2014
Event	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia Duration: 2014 Jun 1 → 2014 Jun 5

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Other

Other	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Country/Territory	Australia
City	Melbourne, VIC
Period	2014/06/01 → 2014/06/05

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2014.6865109

Cite this

Lin, K. Y., Ker, M. D., & Lin, C. Y. (2014). A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 (pp. 237-240). Article 6865109 (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2014.6865109

A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant. / Lin, Kuan Yu; Ker, Ming Dou; Lin, Chun Yu.
2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., 2014. p. 237-240 6865109 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lin, KY, Ker, MD & Lin, CY 2014, A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant. in 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014., 6865109, Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., pp. 237-240, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014, Melbourne, VIC, Australia, 2014/06/01. https://doi.org/10.1109/ISCAS.2014.6865109

Lin KY, Ker MD, Lin CY. A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc. 2014. p. 237-240. 6865109. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS.2014.6865109

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abstract = "A biomedical stimulator with four high-voltagetolerant output channels, combined with on-chip positive high voltage generator, is proposed. For the purpose of integration with other circuit blocks into a system-on-chip (SoC) for cochlear implant biomedical applications, this design has been realized with the 1.8-V/3.3-V transistors in a 0.18-μm CMOS process. This stimulator only needs one single supply voltage of 1.8 V, but the maximum stimulation voltage can be as high as 7 V. The dynamic bias technique and stacked MOS configuration are used to implement this stimulator in the low-voltage CMOS process, without causing the issues of electrical overstress and gate-oxide reliability during circuit operation.",

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A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant

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