A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant

Kuan Yu Lin, Ming Dou Ker, Chun-Yu Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A biomedical stimulator with four high-voltagetolerant output channels, combined with on-chip positive high voltage generator, is proposed. For the purpose of integration with other circuit blocks into a system-on-chip (SoC) for cochlear implant biomedical applications, this design has been realized with the 1.8-V/3.3-V transistors in a 0.18-μm CMOS process. This stimulator only needs one single supply voltage of 1.8 V, but the maximum stimulation voltage can be as high as 7 V. The dynamic bias technique and stacked MOS configuration are used to implement this stimulator in the low-voltage CMOS process, without causing the issues of electrical overstress and gate-oxide reliability during circuit operation.

Original languageEnglish
Title of host publication2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages237-240
Number of pages4
ISBN (Print)9781479934324
DOIs
Publication statusPublished - 2014 Jan 1
Event2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia
Duration: 2014 Jun 12014 Jun 5

Other

Other2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
CountryAustralia
CityMelbourne, VIC
Period14/6/114/6/5

Fingerprint

Cochlear implants
Electric potential
Networks (circuits)
Transistors
Oxides

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Lin, K. Y., Ker, M. D., & Lin, C-Y. (2014). A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 (pp. 237-240). [6865109] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2014.6865109

A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant. / Lin, Kuan Yu; Ker, Ming Dou; Lin, Chun-Yu.

2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., 2014. p. 237-240 6865109.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lin, KY, Ker, MD & Lin, C-Y 2014, A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant. in 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014., 6865109, Institute of Electrical and Electronics Engineers Inc., pp. 237-240, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014, Melbourne, VIC, Australia, 14/6/1. https://doi.org/10.1109/ISCAS.2014.6865109
Lin KY, Ker MD, Lin C-Y. A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc. 2014. p. 237-240. 6865109 https://doi.org/10.1109/ISCAS.2014.6865109
Lin, Kuan Yu ; Ker, Ming Dou ; Lin, Chun-Yu. / A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant. 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., 2014. pp. 237-240
@inproceedings{e37efb821b6c46f5a4b5a299b0b9d776,
title = "A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant",
abstract = "A biomedical stimulator with four high-voltagetolerant output channels, combined with on-chip positive high voltage generator, is proposed. For the purpose of integration with other circuit blocks into a system-on-chip (SoC) for cochlear implant biomedical applications, this design has been realized with the 1.8-V/3.3-V transistors in a 0.18-μm CMOS process. This stimulator only needs one single supply voltage of 1.8 V, but the maximum stimulation voltage can be as high as 7 V. The dynamic bias technique and stacked MOS configuration are used to implement this stimulator in the low-voltage CMOS process, without causing the issues of electrical overstress and gate-oxide reliability during circuit operation.",
author = "Lin, {Kuan Yu} and Ker, {Ming Dou} and Chun-Yu Lin",
year = "2014",
month = "1",
day = "1",
doi = "10.1109/ISCAS.2014.6865109",
language = "English",
isbn = "9781479934324",
pages = "237--240",
booktitle = "2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - GEN

T1 - A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant

AU - Lin, Kuan Yu

AU - Ker, Ming Dou

AU - Lin, Chun-Yu

PY - 2014/1/1

Y1 - 2014/1/1

N2 - A biomedical stimulator with four high-voltagetolerant output channels, combined with on-chip positive high voltage generator, is proposed. For the purpose of integration with other circuit blocks into a system-on-chip (SoC) for cochlear implant biomedical applications, this design has been realized with the 1.8-V/3.3-V transistors in a 0.18-μm CMOS process. This stimulator only needs one single supply voltage of 1.8 V, but the maximum stimulation voltage can be as high as 7 V. The dynamic bias technique and stacked MOS configuration are used to implement this stimulator in the low-voltage CMOS process, without causing the issues of electrical overstress and gate-oxide reliability during circuit operation.

AB - A biomedical stimulator with four high-voltagetolerant output channels, combined with on-chip positive high voltage generator, is proposed. For the purpose of integration with other circuit blocks into a system-on-chip (SoC) for cochlear implant biomedical applications, this design has been realized with the 1.8-V/3.3-V transistors in a 0.18-μm CMOS process. This stimulator only needs one single supply voltage of 1.8 V, but the maximum stimulation voltage can be as high as 7 V. The dynamic bias technique and stacked MOS configuration are used to implement this stimulator in the low-voltage CMOS process, without causing the issues of electrical overstress and gate-oxide reliability during circuit operation.

UR - http://www.scopus.com/inward/record.url?scp=84907398536&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84907398536&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2014.6865109

DO - 10.1109/ISCAS.2014.6865109

M3 - Conference contribution

AN - SCOPUS:84907398536

SN - 9781479934324

SP - 237

EP - 240

BT - 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014

PB - Institute of Electrical and Electronics Engineers Inc.

ER -