A high energy-efficiency SAR ADC based on partial floating capacitor switching technique

Chien Hung Kuo; Cheng En Hsieh

doi:10.1109/ESSCIRC.2011.6045010

A high energy-efficiency SAR ADC based on partial floating capacitor switching technique

Chien Hung Kuo^*, Cheng En Hsieh

^*Corresponding author for this work

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

17 Citations (Scopus)

Abstract

This paper presents a new successive approximation register (SAR) analog-to-digital converter (ADC) with partial floating capacitor switching (PFCS) scheme for low-power data converters. By interchanging the switching order of the largest capacitor with the second largest one the switching energy consumption can be efficiently reduced. From the mathematical calculation result, the proposed technique achieves 96.11% less switching energy compared to the conventional approach. The presented 10-bit PFCS-based SAR ADC is implemented in a CMOS 0.18-μm 1P6M technology. The power consumption of the presented prototype is only 7.16-μW with a sampling rate of 1-MS/s at a supply voltage of 0.9-V and a 21.56-fF/conversion-step figure of merit is achieved.

Original language	English
Title of host publication	ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference
Pages	475-478
Number of pages	4
DOIs	https://doi.org/10.1109/ESSCIRC.2011.6045010
Publication status	Published - 2011
Event	37th European Solid-State Circuits Conference, ESSCIRC 2011 - Helsinki, Finland Duration: 2011 Sept 12 → 2011 Sept 16

Publication series

Name	European Solid-State Circuits Conference
ISSN (Print)	1930-8833

Other

Other	37th European Solid-State Circuits Conference, ESSCIRC 2011
Country/Territory	Finland
City	Helsinki
Period	2011/09/12 → 2011/09/16

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ESSCIRC.2011.6045010

Cite this

Kuo, CH & Hsieh, CE 2011, A high energy-efficiency SAR ADC based on partial floating capacitor switching technique. in ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference., 6045010, European Solid-State Circuits Conference, pp. 475-478, 37th European Solid-State Circuits Conference, ESSCIRC 2011, Helsinki, Finland, 2011/09/12. https://doi.org/10.1109/ESSCIRC.2011.6045010

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title = "A high energy-efficiency SAR ADC based on partial floating capacitor switching technique",

abstract = "This paper presents a new successive approximation register (SAR) analog-to-digital converter (ADC) with partial floating capacitor switching (PFCS) scheme for low-power data converters. By interchanging the switching order of the largest capacitor with the second largest one the switching energy consumption can be efficiently reduced. From the mathematical calculation result, the proposed technique achieves 96.11% less switching energy compared to the conventional approach. The presented 10-bit PFCS-based SAR ADC is implemented in a CMOS 0.18-μm 1P6M technology. The power consumption of the presented prototype is only 7.16-μW with a sampling rate of 1-MS/s at a supply voltage of 0.9-V and a 21.56-fF/conversion-step figure of merit is achieved.",

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AU - Kuo, Chien Hung

AU - Hsieh, Cheng En

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N2 - This paper presents a new successive approximation register (SAR) analog-to-digital converter (ADC) with partial floating capacitor switching (PFCS) scheme for low-power data converters. By interchanging the switching order of the largest capacitor with the second largest one the switching energy consumption can be efficiently reduced. From the mathematical calculation result, the proposed technique achieves 96.11% less switching energy compared to the conventional approach. The presented 10-bit PFCS-based SAR ADC is implemented in a CMOS 0.18-μm 1P6M technology. The power consumption of the presented prototype is only 7.16-μW with a sampling rate of 1-MS/s at a supply voltage of 0.9-V and a 21.56-fF/conversion-step figure of merit is achieved.

AB - This paper presents a new successive approximation register (SAR) analog-to-digital converter (ADC) with partial floating capacitor switching (PFCS) scheme for low-power data converters. By interchanging the switching order of the largest capacitor with the second largest one the switching energy consumption can be efficiently reduced. From the mathematical calculation result, the proposed technique achieves 96.11% less switching energy compared to the conventional approach. The presented 10-bit PFCS-based SAR ADC is implemented in a CMOS 0.18-μm 1P6M technology. The power consumption of the presented prototype is only 7.16-μW with a sampling rate of 1-MS/s at a supply voltage of 0.9-V and a 21.56-fF/conversion-step figure of merit is achieved.

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A high energy-efficiency SAR ADC based on partial floating capacitor switching technique

Abstract

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ASJC Scopus subject areas

UN SDGs

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