A high energy-efficiency SAR ADC based on partial floating capacitor switching technique

Chien-Hung Kuo, Cheng En Hsieh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)

Abstract

This paper presents a new successive approximation register (SAR) analog-to-digital converter (ADC) with partial floating capacitor switching (PFCS) scheme for low-power data converters. By interchanging the switching order of the largest capacitor with the second largest one the switching energy consumption can be efficiently reduced. From the mathematical calculation result, the proposed technique achieves 96.11% less switching energy compared to the conventional approach. The presented 10-bit PFCS-based SAR ADC is implemented in a CMOS 0.18-μm 1P6M technology. The power consumption of the presented prototype is only 7.16-μW with a sampling rate of 1-MS/s at a supply voltage of 0.9-V and a 21.56-fF/conversion-step figure of merit is achieved.

Original languageEnglish
Title of host publicationESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference
Pages475-478
Number of pages4
DOIs
Publication statusPublished - 2011 Dec 12
Event37th European Solid-State Circuits Conference, ESSCIRC 2011 - Helsinki, Finland
Duration: 2011 Sep 122011 Sep 16

Publication series

NameEuropean Solid-State Circuits Conference
ISSN (Print)1930-8833

Other

Other37th European Solid-State Circuits Conference, ESSCIRC 2011
CountryFinland
CityHelsinki
Period11/9/1211/9/16

Fingerprint

Digital to analog conversion
Energy efficiency
Capacitors
Electric power utilization
Energy utilization
Sampling
Electric potential

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Kuo, C-H., & Hsieh, C. E. (2011). A high energy-efficiency SAR ADC based on partial floating capacitor switching technique. In ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference (pp. 475-478). [6045010] (European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIRC.2011.6045010

A high energy-efficiency SAR ADC based on partial floating capacitor switching technique. / Kuo, Chien-Hung; Hsieh, Cheng En.

ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference. 2011. p. 475-478 6045010 (European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kuo, C-H & Hsieh, CE 2011, A high energy-efficiency SAR ADC based on partial floating capacitor switching technique. in ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference., 6045010, European Solid-State Circuits Conference, pp. 475-478, 37th European Solid-State Circuits Conference, ESSCIRC 2011, Helsinki, Finland, 11/9/12. https://doi.org/10.1109/ESSCIRC.2011.6045010
Kuo C-H, Hsieh CE. A high energy-efficiency SAR ADC based on partial floating capacitor switching technique. In ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference. 2011. p. 475-478. 6045010. (European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIRC.2011.6045010
Kuo, Chien-Hung ; Hsieh, Cheng En. / A high energy-efficiency SAR ADC based on partial floating capacitor switching technique. ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference. 2011. pp. 475-478 (European Solid-State Circuits Conference).
@inproceedings{f7325280414847b3af20a191f0900333,
title = "A high energy-efficiency SAR ADC based on partial floating capacitor switching technique",
abstract = "This paper presents a new successive approximation register (SAR) analog-to-digital converter (ADC) with partial floating capacitor switching (PFCS) scheme for low-power data converters. By interchanging the switching order of the largest capacitor with the second largest one the switching energy consumption can be efficiently reduced. From the mathematical calculation result, the proposed technique achieves 96.11{\%} less switching energy compared to the conventional approach. The presented 10-bit PFCS-based SAR ADC is implemented in a CMOS 0.18-μm 1P6M technology. The power consumption of the presented prototype is only 7.16-μW with a sampling rate of 1-MS/s at a supply voltage of 0.9-V and a 21.56-fF/conversion-step figure of merit is achieved.",
author = "Chien-Hung Kuo and Hsieh, {Cheng En}",
year = "2011",
month = "12",
day = "12",
doi = "10.1109/ESSCIRC.2011.6045010",
language = "English",
isbn = "9781457707018",
series = "European Solid-State Circuits Conference",
pages = "475--478",
booktitle = "ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference",

}

TY - GEN

T1 - A high energy-efficiency SAR ADC based on partial floating capacitor switching technique

AU - Kuo, Chien-Hung

AU - Hsieh, Cheng En

PY - 2011/12/12

Y1 - 2011/12/12

N2 - This paper presents a new successive approximation register (SAR) analog-to-digital converter (ADC) with partial floating capacitor switching (PFCS) scheme for low-power data converters. By interchanging the switching order of the largest capacitor with the second largest one the switching energy consumption can be efficiently reduced. From the mathematical calculation result, the proposed technique achieves 96.11% less switching energy compared to the conventional approach. The presented 10-bit PFCS-based SAR ADC is implemented in a CMOS 0.18-μm 1P6M technology. The power consumption of the presented prototype is only 7.16-μW with a sampling rate of 1-MS/s at a supply voltage of 0.9-V and a 21.56-fF/conversion-step figure of merit is achieved.

AB - This paper presents a new successive approximation register (SAR) analog-to-digital converter (ADC) with partial floating capacitor switching (PFCS) scheme for low-power data converters. By interchanging the switching order of the largest capacitor with the second largest one the switching energy consumption can be efficiently reduced. From the mathematical calculation result, the proposed technique achieves 96.11% less switching energy compared to the conventional approach. The presented 10-bit PFCS-based SAR ADC is implemented in a CMOS 0.18-μm 1P6M technology. The power consumption of the presented prototype is only 7.16-μW with a sampling rate of 1-MS/s at a supply voltage of 0.9-V and a 21.56-fF/conversion-step figure of merit is achieved.

UR - http://www.scopus.com/inward/record.url?scp=82955194670&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=82955194670&partnerID=8YFLogxK

U2 - 10.1109/ESSCIRC.2011.6045010

DO - 10.1109/ESSCIRC.2011.6045010

M3 - Conference contribution

AN - SCOPUS:82955194670

SN - 9781457707018

T3 - European Solid-State Circuits Conference

SP - 475

EP - 478

BT - ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference

ER -