A high energy-efficiency SAR ADC based on partial floating capacitor switching technique

Chien-Hung Kuo, Cheng En Hsieh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)

Abstract

This paper presents a new successive approximation register (SAR) analog-to-digital converter (ADC) with partial floating capacitor switching (PFCS) scheme for low-power data converters. By interchanging the switching order of the largest capacitor with the second largest one the switching energy consumption can be efficiently reduced. From the mathematical calculation result, the proposed technique achieves 96.11% less switching energy compared to the conventional approach. The presented 10-bit PFCS-based SAR ADC is implemented in a CMOS 0.18-μm 1P6M technology. The power consumption of the presented prototype is only 7.16-μW with a sampling rate of 1-MS/s at a supply voltage of 0.9-V and a 21.56-fF/conversion-step figure of merit is achieved.

Original languageEnglish
Title of host publicationESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference
Pages475-478
Number of pages4
DOIs
Publication statusPublished - 2011 Dec 12
Event37th European Solid-State Circuits Conference, ESSCIRC 2011 - Helsinki, Finland
Duration: 2011 Sep 122011 Sep 16

Publication series

NameEuropean Solid-State Circuits Conference
ISSN (Print)1930-8833

Other

Other37th European Solid-State Circuits Conference, ESSCIRC 2011
CountryFinland
CityHelsinki
Period11/9/1211/9/16

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Kuo, C-H., & Hsieh, C. E. (2011). A high energy-efficiency SAR ADC based on partial floating capacitor switching technique. In ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference (pp. 475-478). [6045010] (European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIRC.2011.6045010