@inproceedings{70dd41decd73473da770ea7af73ae27b,
title = "A fast-locking DLL-based frequency multiplier for wide-range operation",
abstract = "In this paper, a fast-locking delay-locked loop (DLL)-based frequency multiplier for wide-range operation is proposed. A programmable charging circuit (PCC) to the loop filter is developed to accelerate the locking time of DLL. In the presented DLL, the pseudo-differential delay cell is adopted in the voltage-controlled delay line (VCDL) for the suppression of the common-mode noise. Five clock cycles of the least lock time can be reached in the presented DLL. A new DLL-based frequency multiplier with less active devices is also proposed to promote the operating frequency range from 200 MHz to 2.1 GHz. The simulated cycle-to-cycle jitter of the DLL is 31 ps at 320 MHz of the reference input. The prototype circuit has been fabricated in a 0.18 μm 1P6M CMOS technology. The core area excluding PADs is 0.36×0.37 mm2. The power consumption of the proposed DLL is 24 mW from a 1.8 V of supply voltage.",
keywords = "Clock generator, Delay-locked loops (DLLs), Fast-locking DLL, Frequency multiplier, Programmable charging circuit (PCC)",
author = "Kuo, {Chien Hung} and Chien, {Ching Shan} and Lin, {Meng Feng} and Tsai, {Yen Cheng}",
year = "2007",
language = "English",
isbn = "9780889866706",
series = "Proceedings of the Fifth IASTED International Conference on Circuits, Signals, and Systems, CSS 2007",
pages = "105--110",
booktitle = "Proceedings of the Fifth IASTED International Conference on Circuits, Signals, and Systems, CSS 2007",
note = "5th IASTED International Conference on Circuits, Signals, and Systems, CSS 2007 ; Conference date: 02-07-2007 Through 04-07-2007",
}