A fast-locking DLL-based frequency multiplier for wide-range operation

Chien-Hung Kuo, Ching Shan Chien, Meng Feng Lin, Yen Cheng Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, a fast-locking delay-locked loop (DLL)-based frequency multiplier for wide-range operation is proposed. A programmable charging circuit (PCC) to the loop filter is developed to accelerate the locking time of DLL. In the presented DLL, the pseudo-differential delay cell is adopted in the voltage-controlled delay line (VCDL) for the suppression of the common-mode noise. Five clock cycles of the least lock time can be reached in the presented DLL. A new DLL-based frequency multiplier with less active devices is also proposed to promote the operating frequency range from 200 MHz to 2.1 GHz. The simulated cycle-to-cycle jitter of the DLL is 31 ps at 320 MHz of the reference input. The prototype circuit has been fabricated in a 0.18 μm 1P6M CMOS technology. The core area excluding PADs is 0.36×0.37 mm2. The power consumption of the proposed DLL is 24 mW from a 1.8 V of supply voltage.

Original languageEnglish
Title of host publicationProceedings of the Fifth IASTED International Conference on Circuits, Signals, and Systems, CSS 2007
Pages105-110
Number of pages6
Publication statusPublished - 2007 Dec 1
Event5th IASTED International Conference on Circuits, Signals, and Systems, CSS 2007 - Banff, AB, Canada
Duration: 2007 Jul 22007 Jul 4

Publication series

NameProceedings of the Fifth IASTED International Conference on Circuits, Signals, and Systems, CSS 2007

Other

Other5th IASTED International Conference on Circuits, Signals, and Systems, CSS 2007
CountryCanada
CityBanff, AB
Period07/7/207/7/4

Fingerprint

Frequency multiplying circuits
Networks (circuits)
Electric delay lines
Electric potential
Jitter
Clocks
Electric power utilization

Keywords

  • Clock generator
  • Delay-locked loops (DLLs)
  • Fast-locking DLL
  • Frequency multiplier
  • Programmable charging circuit (PCC)

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Kuo, C-H., Chien, C. S., Lin, M. F., & Tsai, Y. C. (2007). A fast-locking DLL-based frequency multiplier for wide-range operation. In Proceedings of the Fifth IASTED International Conference on Circuits, Signals, and Systems, CSS 2007 (pp. 105-110). (Proceedings of the Fifth IASTED International Conference on Circuits, Signals, and Systems, CSS 2007).

A fast-locking DLL-based frequency multiplier for wide-range operation. / Kuo, Chien-Hung; Chien, Ching Shan; Lin, Meng Feng; Tsai, Yen Cheng.

Proceedings of the Fifth IASTED International Conference on Circuits, Signals, and Systems, CSS 2007. 2007. p. 105-110 (Proceedings of the Fifth IASTED International Conference on Circuits, Signals, and Systems, CSS 2007).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kuo, C-H, Chien, CS, Lin, MF & Tsai, YC 2007, A fast-locking DLL-based frequency multiplier for wide-range operation. in Proceedings of the Fifth IASTED International Conference on Circuits, Signals, and Systems, CSS 2007. Proceedings of the Fifth IASTED International Conference on Circuits, Signals, and Systems, CSS 2007, pp. 105-110, 5th IASTED International Conference on Circuits, Signals, and Systems, CSS 2007, Banff, AB, Canada, 07/7/2.
Kuo C-H, Chien CS, Lin MF, Tsai YC. A fast-locking DLL-based frequency multiplier for wide-range operation. In Proceedings of the Fifth IASTED International Conference on Circuits, Signals, and Systems, CSS 2007. 2007. p. 105-110. (Proceedings of the Fifth IASTED International Conference on Circuits, Signals, and Systems, CSS 2007).
Kuo, Chien-Hung ; Chien, Ching Shan ; Lin, Meng Feng ; Tsai, Yen Cheng. / A fast-locking DLL-based frequency multiplier for wide-range operation. Proceedings of the Fifth IASTED International Conference on Circuits, Signals, and Systems, CSS 2007. 2007. pp. 105-110 (Proceedings of the Fifth IASTED International Conference on Circuits, Signals, and Systems, CSS 2007).
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N2 - In this paper, a fast-locking delay-locked loop (DLL)-based frequency multiplier for wide-range operation is proposed. A programmable charging circuit (PCC) to the loop filter is developed to accelerate the locking time of DLL. In the presented DLL, the pseudo-differential delay cell is adopted in the voltage-controlled delay line (VCDL) for the suppression of the common-mode noise. Five clock cycles of the least lock time can be reached in the presented DLL. A new DLL-based frequency multiplier with less active devices is also proposed to promote the operating frequency range from 200 MHz to 2.1 GHz. The simulated cycle-to-cycle jitter of the DLL is 31 ps at 320 MHz of the reference input. The prototype circuit has been fabricated in a 0.18 μm 1P6M CMOS technology. The core area excluding PADs is 0.36×0.37 mm2. The power consumption of the proposed DLL is 24 mW from a 1.8 V of supply voltage.

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