A delta-sigma modulator-based class-D amplifier

Chien Hung Kuo; Sheng Chi Lin

doi:10.1109/GCCE.2016.7800440

A delta-sigma modulator-based class-D amplifier

Chien Hung Kuo, Sheng Chi Lin

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

A new architecture of class-D amplifier with a multibit delta-sigma modulator control is presented in this paper. In the presented amplifier, the 3-bit 8-level digital outputs of the second-order delta-sigma modulator are utilized to generate switching signals with different pulse widths for the class-D power amplifier. A closed-loop class-D amplifier is adopted by feeding the analog output signal from the power stage to the input to improve the linearity. The presented class-D amplifier is simulated with TSMC 0.18-μm CMOS process. The SNDR of the proposed amplifier is 78 dB within a 25 kHz signal bandwidth under a sample rate of 2.56 MHz. The THD is 0.01% at a power consumption of 140 mW.

Original language	English
Title of host publication	2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509023332
DOIs	https://doi.org/10.1109/GCCE.2016.7800440
Publication status	Published - 2016 Dec 27
Event	5th IEEE Global Conference on Consumer Electronics, GCCE 2016 - Kyoto, Japan Duration: 2016 Oct 11 → 2016 Oct 14

Publication series

Name	2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016

Other

Other	5th IEEE Global Conference on Consumer Electronics, GCCE 2016
Country/Territory	Japan
City	Kyoto
Period	2016/10/11 → 2016/10/14

Keywords

Class-D Amplifier
Delta-Sigma Class-D Amplifier
Switching Amplifier

ASJC Scopus subject areas

Signal Processing
Electrical and Electronic Engineering
Computer Science Applications
Hardware and Architecture
Instrumentation

Access to Document

10.1109/GCCE.2016.7800440

Cite this

A delta-sigma modulator-based class-D amplifier. / Kuo, Chien Hung; Lin, Sheng Chi.
2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7800440 (2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kuo, CH & Lin, SC 2016, A delta-sigma modulator-based class-D amplifier. in 2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016., 7800440, 2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016, Institute of Electrical and Electronics Engineers Inc., 5th IEEE Global Conference on Consumer Electronics, GCCE 2016, Kyoto, Japan, 2016/10/11. https://doi.org/10.1109/GCCE.2016.7800440

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abstract = "A new architecture of class-D amplifier with a multibit delta-sigma modulator control is presented in this paper. In the presented amplifier, the 3-bit 8-level digital outputs of the second-order delta-sigma modulator are utilized to generate switching signals with different pulse widths for the class-D power amplifier. A closed-loop class-D amplifier is adopted by feeding the analog output signal from the power stage to the input to improve the linearity. The presented class-D amplifier is simulated with TSMC 0.18-μm CMOS process. The SNDR of the proposed amplifier is 78 dB within a 25 kHz signal bandwidth under a sample rate of 2.56 MHz. The THD is 0.01% at a power consumption of 140 mW.",

keywords = "Class-D Amplifier, Delta-Sigma Class-D Amplifier, Switching Amplifier",

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AU - Kuo, Chien Hung

AU - Lin, Sheng Chi

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Y1 - 2016/12/27

N2 - A new architecture of class-D amplifier with a multibit delta-sigma modulator control is presented in this paper. In the presented amplifier, the 3-bit 8-level digital outputs of the second-order delta-sigma modulator are utilized to generate switching signals with different pulse widths for the class-D power amplifier. A closed-loop class-D amplifier is adopted by feeding the analog output signal from the power stage to the input to improve the linearity. The presented class-D amplifier is simulated with TSMC 0.18-μm CMOS process. The SNDR of the proposed amplifier is 78 dB within a 25 kHz signal bandwidth under a sample rate of 2.56 MHz. The THD is 0.01% at a power consumption of 140 mW.

AB - A new architecture of class-D amplifier with a multibit delta-sigma modulator control is presented in this paper. In the presented amplifier, the 3-bit 8-level digital outputs of the second-order delta-sigma modulator are utilized to generate switching signals with different pulse widths for the class-D power amplifier. A closed-loop class-D amplifier is adopted by feeding the analog output signal from the power stage to the input to improve the linearity. The presented class-D amplifier is simulated with TSMC 0.18-μm CMOS process. The SNDR of the proposed amplifier is 78 dB within a 25 kHz signal bandwidth under a sample rate of 2.56 MHz. The THD is 0.01% at a power consumption of 140 mW.

KW - Class-D Amplifier

KW - Delta-Sigma Class-D Amplifier

KW - Switching Amplifier

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ER -

A delta-sigma modulator-based class-D amplifier

Abstract

Publication series

Other

Keywords

ASJC Scopus subject areas

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