A Clock-Free 200MS/s 10-bit Time-Interleaved SAR ADC

Chien Hung Kuo, Zih Jyun Luo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, a clock-free 200-MS/s 10-bit time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) is proposed. The presented SAR ADC can generate required clock by itself while an active signal is asserted. In the presented TI structure, two SAR ADCs are alternated with entering sample and comparison phases by the control circuit, and thus the equivalent sample rate can be doubled. The presented ADC is simulated under TSMC 90nm 1P9M CMOS process. Under a supply voltage of 1.2-V and an equivalent sampling rate of 200-MS/s, the resulted SNDR of the proposed ADC is 58.94 dB, which is equivalent to the ENOB of 9.50-bit. The simulated DNL and INL are within 0.735 /-0.404 and 0.734 /-0.552, respectively.

Original languageEnglish
Title of host publicationProceedings of the 26th International Conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2019
EditorsAndrzej Napieralski
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages133-136
Number of pages4
ISBN (Electronic)9788363578152
DOIs
Publication statusPublished - 2019 Jun
Event26th International Conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2019 - Rzeszow, Poland
Duration: 2019 Jun 272019 Jun 29

Publication series

NameProceedings of the 26th International Conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2019

Conference

Conference26th International Conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2019
CountryPoland
CityRzeszow
Period19/6/2719/6/29

Keywords

  • analog-To-digital converters
  • clock-free
  • successive approximation register
  • time-interleaved

ASJC Scopus subject areas

  • Hardware and Architecture
  • Energy Engineering and Power Technology
  • Electrical and Electronic Engineering
  • Instrumentation

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  • Cite this

    Kuo, C. H., & Luo, Z. J. (2019). A Clock-Free 200MS/s 10-bit Time-Interleaved SAR ADC. In A. Napieralski (Ed.), Proceedings of the 26th International Conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2019 (pp. 133-136). [8787144] (Proceedings of the 26th International Conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/MIXDES.2019.8787144