A center-aligned digital pulse-width modulator for envelope modulation of polar transmitters

Chien-Hung Kuo; Cin De Jhang

doi:10.1109/VLSI-SoC.2013.6673314

A center-aligned digital pulse-width modulator for envelope modulation of polar transmitters

Chien-Hung Kuo, Cin De Jhang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents a center-aligned hybrid digital pulse-width modulator for the envelope modulation of polar transmitters [1]. To obtain better noise figure of the outputs, a 128-phase delay-locked loop is used to generate center-aligned output pulses having 64 different pulse widths for 6-bit signal input. To reduce the number of delay cells in the multi-phase DLL, a simple counter is used to separate the output phases of DLL into rise and fall parts. The proposed digital pulse-width modulator is simulated in TSMC 90nm 1P9M process. The power consumption is 0.85 mW at a 92.16 MHz input reference frequency and a supply voltage of 1.2V.

Original language	English
Title of host publication	2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings
Publisher	IEEE Computer Society
Pages	386-389
Number of pages	4
ISBN (Print)	9781479905249
DOIs	https://doi.org/10.1109/VLSI-SoC.2013.6673314
Publication status	Published - 2013 Jan 1
Event	2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Istanbul, Turkey Duration: 2013 Oct 7 → 2013 Oct 9

Publication series

Name	IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
ISSN (Print)	2324-8432
ISSN (Electronic)	2324-8440

Other

Other	2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013
Country/Territory	Turkey
City	Istanbul
Period	2013/10/07 → 2013/10/09

Keywords

DPWM
Envelope modulation
LTE polar modulation transmitter

ASJC Scopus subject areas

Hardware and Architecture
Software
Electrical and Electronic Engineering

Access to Document

10.1109/VLSI-SoC.2013.6673314

Cite this

Kuo, C-H., & Jhang, C. D. (2013). A center-aligned digital pulse-width modulator for envelope modulation of polar transmitters. In 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings (pp. 386-389). [6673314] (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC). IEEE Computer Society. https://doi.org/10.1109/VLSI-SoC.2013.6673314

A center-aligned digital pulse-width modulator for envelope modulation of polar transmitters. / Kuo, Chien-Hung; Jhang, Cin De.

2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings. IEEE Computer Society, 2013. p. 386-389 6673314 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kuo, C-H & Jhang, CD 2013, A center-aligned digital pulse-width modulator for envelope modulation of polar transmitters. in 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings., 6673314, IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, IEEE Computer Society, pp. 386-389, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013, Istanbul, Turkey, 2013/10/07. https://doi.org/10.1109/VLSI-SoC.2013.6673314

Kuo C-H, Jhang CD. A center-aligned digital pulse-width modulator for envelope modulation of polar transmitters. In 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings. IEEE Computer Society. 2013. p. 386-389. 6673314. (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC). https://doi.org/10.1109/VLSI-SoC.2013.6673314

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A center-aligned digital pulse-width modulator for envelope modulation of polar transmitters

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Keywords

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