TY - GEN
T1 - A center-aligned digital pulse-width modulator for envelope modulation of polar transmitters
AU - Kuo, Chien-Hung
AU - Jhang, Cin De
PY - 2013/1/1
Y1 - 2013/1/1
N2 - This paper presents a center-aligned hybrid digital pulse-width modulator for the envelope modulation of polar transmitters [1]. To obtain better noise figure of the outputs, a 128-phase delay-locked loop is used to generate center-aligned output pulses having 64 different pulse widths for 6-bit signal input. To reduce the number of delay cells in the multi-phase DLL, a simple counter is used to separate the output phases of DLL into rise and fall parts. The proposed digital pulse-width modulator is simulated in TSMC 90nm 1P9M process. The power consumption is 0.85 mW at a 92.16 MHz input reference frequency and a supply voltage of 1.2V.
AB - This paper presents a center-aligned hybrid digital pulse-width modulator for the envelope modulation of polar transmitters [1]. To obtain better noise figure of the outputs, a 128-phase delay-locked loop is used to generate center-aligned output pulses having 64 different pulse widths for 6-bit signal input. To reduce the number of delay cells in the multi-phase DLL, a simple counter is used to separate the output phases of DLL into rise and fall parts. The proposed digital pulse-width modulator is simulated in TSMC 90nm 1P9M process. The power consumption is 0.85 mW at a 92.16 MHz input reference frequency and a supply voltage of 1.2V.
KW - DPWM
KW - Envelope modulation
KW - LTE polar modulation transmitter
UR - http://www.scopus.com/inward/record.url?scp=84899516621&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84899516621&partnerID=8YFLogxK
U2 - 10.1109/VLSI-SoC.2013.6673314
DO - 10.1109/VLSI-SoC.2013.6673314
M3 - Conference contribution
AN - SCOPUS:84899516621
SN - 9781479905249
T3 - IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
SP - 386
EP - 389
BT - 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings
PB - IEEE Computer Society
T2 - 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013
Y2 - 7 October 2013 through 9 October 2013
ER -