A center-aligned digital pulse-width modulator for envelope modulation of polar transmitters

Chien-Hung Kuo, Cin De Jhang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a center-aligned hybrid digital pulse-width modulator for the envelope modulation of polar transmitters [1]. To obtain better noise figure of the outputs, a 128-phase delay-locked loop is used to generate center-aligned output pulses having 64 different pulse widths for 6-bit signal input. To reduce the number of delay cells in the multi-phase DLL, a simple counter is used to separate the output phases of DLL into rise and fall parts. The proposed digital pulse-width modulator is simulated in TSMC 90nm 1P9M process. The power consumption is 0.85 mW at a 92.16 MHz input reference frequency and a supply voltage of 1.2V.

Original languageEnglish
Title of host publication2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings
PublisherIEEE Computer Society
Pages386-389
Number of pages4
ISBN (Print)9781479905249
DOIs
Publication statusPublished - 2013 Jan 1
Event2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Istanbul, Turkey
Duration: 2013 Oct 72013 Oct 9

Publication series

NameIEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
ISSN (Print)2324-8432
ISSN (Electronic)2324-8440

Other

Other2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013
CountryTurkey
CityIstanbul
Period13/10/713/10/9

Keywords

  • DPWM
  • Envelope modulation
  • LTE polar modulation transmitter

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A center-aligned digital pulse-width modulator for envelope modulation of polar transmitters'. Together they form a unique fingerprint.

  • Cite this

    Kuo, C-H., & Jhang, C. D. (2013). A center-aligned digital pulse-width modulator for envelope modulation of polar transmitters. In 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings (pp. 386-389). [6673314] (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC). IEEE Computer Society. https://doi.org/10.1109/VLSI-SoC.2013.6673314