TY - GEN

T1 - A bond graph representation of p-n junction diode using VHDL-AMS

AU - Lin, Chung Chieh

AU - Hong, Chin-Ming

PY - 2012/11/27

Y1 - 2012/11/27

N2 - This study focuses on the p-n junction diode modeling and simulation using bond graphs and VHDL-AMS. The bond graph modeling technique has been given an accommodated model for the interaction of power between elements on a system. The power flow is briefly sketched in the bond graph and the state equations are formulated directly from this graphical representation. Bond graph modeling is largely employed nowadays, and new techniques for structural analysis, model reduction as well as a certain number of software packages using bond graph have been developed. The bond graph methodology is a way to get a p-n junction diode model with important parameters to know the performance. VHDL is a modeling language which dedicates the discrete description to digital electronic hardware. Its extension VHDL-AMS allows modeling analogue subsystems and describing signal flow on a functional level. VHDL-AMS can be used as a unified modeling language for combined discrete-continuous system simulation. Once bond graphs are established, they can be easily described in VHDL-AMS. It will be possible to implement those models in any VHDL-AMS simulator. The system modeling yields equations, i.e. algebra and differential equations, and these equations have to be implemented into a reference simulator. The model is developed and simulated with the VHDL-AMS language under Dolphin SMASH environment.

AB - This study focuses on the p-n junction diode modeling and simulation using bond graphs and VHDL-AMS. The bond graph modeling technique has been given an accommodated model for the interaction of power between elements on a system. The power flow is briefly sketched in the bond graph and the state equations are formulated directly from this graphical representation. Bond graph modeling is largely employed nowadays, and new techniques for structural analysis, model reduction as well as a certain number of software packages using bond graph have been developed. The bond graph methodology is a way to get a p-n junction diode model with important parameters to know the performance. VHDL is a modeling language which dedicates the discrete description to digital electronic hardware. Its extension VHDL-AMS allows modeling analogue subsystems and describing signal flow on a functional level. VHDL-AMS can be used as a unified modeling language for combined discrete-continuous system simulation. Once bond graphs are established, they can be easily described in VHDL-AMS. It will be possible to implement those models in any VHDL-AMS simulator. The system modeling yields equations, i.e. algebra and differential equations, and these equations have to be implemented into a reference simulator. The model is developed and simulated with the VHDL-AMS language under Dolphin SMASH environment.

KW - Bond graph

KW - P-n junction diode

KW - VHDL-AMS

UR - http://www.scopus.com/inward/record.url?scp=84869792259&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84869792259&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:84869792259

SN - 9781618399854

T3 - Proceedings of the 2012 - 10th International Conference on Bond Graph Modeling and Simulation, ICBGM'12, Part of SummerSim 2012 Multiconference

SP - 222

EP - 229

BT - Proceedings of the 2012 - 10th International Conference on Bond Graph Modeling and Simulation, ICBGM'12, Part of SummerSim 2012 Multiconference

T2 - 10th International Conference on Bond Graph Modeling and Simulation, ICBGM 2012, Part of SummerSim 2012 Multiconference

Y2 - 8 July 2012 through 11 July 2012

ER -