Abstract
In this paper, a low-voltage switched-opamp-based 2-2 cascaded switehed-capacitor delta-sigma modulator in a 0.18-μm 1P6M CMOS technology is presented. The fourth-order modulator is realized using a low-distortion feed-forward topology to promote its linearity and dynamic range. The presented modulator can be operated in a wide range of supply voltage from 1.8V to 0.9V. The switched-opamp with double output stage is utilized to combine with the double-sampling technique so that the effective clocking rate can be reduced, thus also relaxing the requirement of opamp. The modulator achieves a 91 dB of SNDR within 24 kHz signal bandwidth under a 2 MHz of clocking rate. The total power consumption of this modulator is 0.86 mW under a 1V supply voltage and the chip core area is 1.57mm2.
Original language | English |
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Title of host publication | Proceedings of the Fourth IASTED International Conference on Circuits, Signals, and Systems, CSS 2006 |
Pages | 199-204 |
Number of pages | 6 |
Publication status | Published - 2006 Dec 1 |
Externally published | Yes |
Event | 4th IASTED International Conference on Circuits, Signals, and Systems, CSS 2006 - San Francisco, CA, United States Duration: 2006 Nov 20 → 2006 Nov 22 |
Other
Other | 4th IASTED International Conference on Circuits, Signals, and Systems, CSS 2006 |
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Country | United States |
City | San Francisco, CA |
Period | 2006/11/20 → 2006/11/22 |
Keywords
- Analog-to-digital converters
- Delta-sigma modulators
- Low-voltage
- Switched-opamp
- Switehed-capacitor circuits
ASJC Scopus subject areas
- Control and Systems Engineering
- Electrical and Electronic Engineering