A 91dB SOP-based low-voltage low-distortion fourth-order 2-2 cascaded delta-sigma modulator

Chien Hung Kuo, Shuo Chau Chen, Kang Shuo Chang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

In this paper, a low-voltage switched-opamp-based 2-2 cascaded switehed-capacitor delta-sigma modulator in a 0.18-μm 1P6M CMOS technology is presented. The fourth-order modulator is realized using a low-distortion feed-forward topology to promote its linearity and dynamic range. The presented modulator can be operated in a wide range of supply voltage from 1.8V to 0.9V. The switched-opamp with double output stage is utilized to combine with the double-sampling technique so that the effective clocking rate can be reduced, thus also relaxing the requirement of opamp. The modulator achieves a 91 dB of SNDR within 24 kHz signal bandwidth under a 2 MHz of clocking rate. The total power consumption of this modulator is 0.86 mW under a 1V supply voltage and the chip core area is 1.57mm2.

Original languageEnglish
Title of host publicationProceedings of the Fourth IASTED International Conference on Circuits, Signals, and Systems, CSS 2006
Pages199-204
Number of pages6
Publication statusPublished - 2006 Dec 1
Externally publishedYes
Event4th IASTED International Conference on Circuits, Signals, and Systems, CSS 2006 - San Francisco, CA, United States
Duration: 2006 Nov 20 → 2006 Nov 22

Other

Other4th IASTED International Conference on Circuits, Signals, and Systems, CSS 2006
CountryUnited States
CitySan Francisco, CA
Period06/11/20 → 06/11/22

Fingerprint

Modulators
Operational amplifiers
Electric potential
Electric power utilization
Capacitors
Topology
Sampling
Bandwidth

Keywords

  • Analog-to-digital converters
  • Delta-sigma modulators
  • Low-voltage
  • Switched-opamp
  • Switehed-capacitor circuits

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Kuo, C. H., Chen, S. C., & Chang, K. S. (2006). A 91dB SOP-based low-voltage low-distortion fourth-order 2-2 cascaded delta-sigma modulator. In Proceedings of the Fourth IASTED International Conference on Circuits, Signals, and Systems, CSS 2006 (pp. 199-204)

A 91dB SOP-based low-voltage low-distortion fourth-order 2-2 cascaded delta-sigma modulator. / Kuo, Chien Hung; Chen, Shuo Chau; Chang, Kang Shuo.

Proceedings of the Fourth IASTED International Conference on Circuits, Signals, and Systems, CSS 2006. 2006. p. 199-204.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kuo, CH, Chen, SC & Chang, KS 2006, A 91dB SOP-based low-voltage low-distortion fourth-order 2-2 cascaded delta-sigma modulator. in Proceedings of the Fourth IASTED International Conference on Circuits, Signals, and Systems, CSS 2006. pp. 199-204, 4th IASTED International Conference on Circuits, Signals, and Systems, CSS 2006, San Francisco, CA, United States, 06/11/20.
Kuo CH, Chen SC, Chang KS. A 91dB SOP-based low-voltage low-distortion fourth-order 2-2 cascaded delta-sigma modulator. In Proceedings of the Fourth IASTED International Conference on Circuits, Signals, and Systems, CSS 2006. 2006. p. 199-204
Kuo, Chien Hung ; Chen, Shuo Chau ; Chang, Kang Shuo. / A 91dB SOP-based low-voltage low-distortion fourth-order 2-2 cascaded delta-sigma modulator. Proceedings of the Fourth IASTED International Conference on Circuits, Signals, and Systems, CSS 2006. 2006. pp. 199-204
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N2 - In this paper, a low-voltage switched-opamp-based 2-2 cascaded switehed-capacitor delta-sigma modulator in a 0.18-μm 1P6M CMOS technology is presented. The fourth-order modulator is realized using a low-distortion feed-forward topology to promote its linearity and dynamic range. The presented modulator can be operated in a wide range of supply voltage from 1.8V to 0.9V. The switched-opamp with double output stage is utilized to combine with the double-sampling technique so that the effective clocking rate can be reduced, thus also relaxing the requirement of opamp. The modulator achieves a 91 dB of SNDR within 24 kHz signal bandwidth under a 2 MHz of clocking rate. The total power consumption of this modulator is 0.86 mW under a 1V supply voltage and the chip core area is 1.57mm2.

AB - In this paper, a low-voltage switched-opamp-based 2-2 cascaded switehed-capacitor delta-sigma modulator in a 0.18-μm 1P6M CMOS technology is presented. The fourth-order modulator is realized using a low-distortion feed-forward topology to promote its linearity and dynamic range. The presented modulator can be operated in a wide range of supply voltage from 1.8V to 0.9V. The switched-opamp with double output stage is utilized to combine with the double-sampling technique so that the effective clocking rate can be reduced, thus also relaxing the requirement of opamp. The modulator achieves a 91 dB of SNDR within 24 kHz signal bandwidth under a 2 MHz of clocking rate. The total power consumption of this modulator is 0.86 mW under a 1V supply voltage and the chip core area is 1.57mm2.

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