A 91dB SOP-based low-voltage low-distortion fourth-order 2-2 cascaded delta-sigma modulator

Chien Hung Kuo; Shuo Chau Chen; Kang Shuo Chang

A 91dB SOP-based low-voltage low-distortion fourth-order 2-2 cascaded delta-sigma modulator

Chien Hung Kuo, Shuo Chau Chen, Kang Shuo Chang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, a low-voltage switched-opamp-based 2-2 cascaded switehed-capacitor delta-sigma modulator in a 0.18-μm 1P6M CMOS technology is presented. The fourth-order modulator is realized using a low-distortion feed-forward topology to promote its linearity and dynamic range. The presented modulator can be operated in a wide range of supply voltage from 1.8V to 0.9V. The switched-opamp with double output stage is utilized to combine with the double-sampling technique so that the effective clocking rate can be reduced, thus also relaxing the requirement of opamp. The modulator achieves a 91 dB of SNDR within 24 kHz signal bandwidth under a 2 MHz of clocking rate. The total power consumption of this modulator is 0.86 mW under a 1V supply voltage and the chip core area is 1.57mm².

Original language	English
Title of host publication	Proceedings of the Fourth IASTED International Conference on Circuits, Signals, and Systems, CSS 2006
Pages	199-204
Number of pages	6
Publication status	Published - 2006 Dec 1
Externally published	Yes
Event	4th IASTED International Conference on Circuits, Signals, and Systems, CSS 2006 - San Francisco, CA, United States Duration: 2006 Nov 20 → 2006 Nov 22

Other

Other	4th IASTED International Conference on Circuits, Signals, and Systems, CSS 2006
Country	United States
City	San Francisco, CA
Period	2006/11/20 → 2006/11/22

Keywords

Analog-to-digital converters
Delta-sigma modulators
Low-voltage
Switched-opamp
Switehed-capacitor circuits

ASJC Scopus subject areas

Control and Systems Engineering
Electrical and Electronic Engineering

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Cite this

Kuo, CH, Chen, SC & Chang, KS 2006, A 91dB SOP-based low-voltage low-distortion fourth-order 2-2 cascaded delta-sigma modulator. in Proceedings of the Fourth IASTED International Conference on Circuits, Signals, and Systems, CSS 2006. pp. 199-204, 4th IASTED International Conference on Circuits, Signals, and Systems, CSS 2006, San Francisco, CA, United States, 2006/11/20.

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title = "A 91dB SOP-based low-voltage low-distortion fourth-order 2-2 cascaded delta-sigma modulator",

abstract = "In this paper, a low-voltage switched-opamp-based 2-2 cascaded switehed-capacitor delta-sigma modulator in a 0.18-μm 1P6M CMOS technology is presented. The fourth-order modulator is realized using a low-distortion feed-forward topology to promote its linearity and dynamic range. The presented modulator can be operated in a wide range of supply voltage from 1.8V to 0.9V. The switched-opamp with double output stage is utilized to combine with the double-sampling technique so that the effective clocking rate can be reduced, thus also relaxing the requirement of opamp. The modulator achieves a 91 dB of SNDR within 24 kHz signal bandwidth under a 2 MHz of clocking rate. The total power consumption of this modulator is 0.86 mW under a 1V supply voltage and the chip core area is 1.57mm2.",

keywords = "Analog-to-digital converters, Delta-sigma modulators, Low-voltage, Switched-opamp, Switehed-capacitor circuits",

author = "Kuo, {Chien Hung} and Chen, {Shuo Chau} and Chang, {Kang Shuo}",

year = "2006",

month = dec,

day = "1",

language = "English",

isbn = "9780889866072",

pages = "199--204",

booktitle = "Proceedings of the Fourth IASTED International Conference on Circuits, Signals, and Systems, CSS 2006",

note = "4th IASTED International Conference on Circuits, Signals, and Systems, CSS 2006 ; Conference date: 20-11-2006 Through 22-11-2006",

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TY - GEN

T1 - A 91dB SOP-based low-voltage low-distortion fourth-order 2-2 cascaded delta-sigma modulator

AU - Kuo, Chien Hung

AU - Chen, Shuo Chau

AU - Chang, Kang Shuo

PY - 2006/12/1

Y1 - 2006/12/1

N2 - In this paper, a low-voltage switched-opamp-based 2-2 cascaded switehed-capacitor delta-sigma modulator in a 0.18-μm 1P6M CMOS technology is presented. The fourth-order modulator is realized using a low-distortion feed-forward topology to promote its linearity and dynamic range. The presented modulator can be operated in a wide range of supply voltage from 1.8V to 0.9V. The switched-opamp with double output stage is utilized to combine with the double-sampling technique so that the effective clocking rate can be reduced, thus also relaxing the requirement of opamp. The modulator achieves a 91 dB of SNDR within 24 kHz signal bandwidth under a 2 MHz of clocking rate. The total power consumption of this modulator is 0.86 mW under a 1V supply voltage and the chip core area is 1.57mm2.

AB - In this paper, a low-voltage switched-opamp-based 2-2 cascaded switehed-capacitor delta-sigma modulator in a 0.18-μm 1P6M CMOS technology is presented. The fourth-order modulator is realized using a low-distortion feed-forward topology to promote its linearity and dynamic range. The presented modulator can be operated in a wide range of supply voltage from 1.8V to 0.9V. The switched-opamp with double output stage is utilized to combine with the double-sampling technique so that the effective clocking rate can be reduced, thus also relaxing the requirement of opamp. The modulator achieves a 91 dB of SNDR within 24 kHz signal bandwidth under a 2 MHz of clocking rate. The total power consumption of this modulator is 0.86 mW under a 1V supply voltage and the chip core area is 1.57mm2.

KW - Analog-to-digital converters

KW - Delta-sigma modulators

KW - Low-voltage

KW - Switched-opamp

KW - Switehed-capacitor circuits

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M3 - Conference contribution

AN - SCOPUS:38349136755

SN - 9780889866072

SP - 199

EP - 204

BT - Proceedings of the Fourth IASTED International Conference on Circuits, Signals, and Systems, CSS 2006

T2 - 4th IASTED International Conference on Circuits, Signals, and Systems, CSS 2006

Y2 - 20 November 2006 through 22 November 2006

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