A 7.5-12 GHz divide-by-256/260/264/268 multi-modulus frequency divider with broadband and high-speed is demonstrated in this paper. The divider is implemented in standard 0.18-μm 1P6M CMOS technology. The frequency divider is composed of a divide-by-4 prescaler, a divide-by-4/5 dual-modulus divider, a divide-by-16 counter, and a digital control logic. Utilizing a CML without tail current source and a modified D-Flip-Flip (DFF) merged with NAND gate function. The operation frequency of the divider is from 7.5-12 GHz via an input signal power of 0 dBm. To further extend the operation frequency, we raise the input signal power of the divider. Providing an input signal power of 16 dBm, an extended operation frequency of the divider from 5 GHz to 13.3 GHz can be achieved. The lowest input sensitivity is about-15 dBm at 8 ∼ 9 GHz. The power consumption of whole divider is about 28.1 mW. The chip size is 0.45 × 0.66 mm 2 including all test pads.