A 7-12 GHz multi-modulus frequency divider

Jeng Han Tsai*, Yi Wei Chung, Hung Da Shih, Jian Ping Chou

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)


A 7-12 GHz divide-by-256/260/264/268 multi-modulus frequency divider chain is designed and implemented in 0.18-μm CMOS technology. The frequency divider chain consists of a divide-by-4 divider, a divide-by-4/5 dual-modulus divider, a divide-by-16 counter, and digital control logic circuits. To speed up the operating frequency, a current mode logic (CML) divider without tail current source and a modified D-Flip-Flip (DFF) merged with NAND gate function are adopted. The multi-modulus frequency divider chain demonstrates high operating frequency of 7 GHz to 12 GHz while maintaining reasonable dc power consumption of 19.95 mW.

Original languageEnglish
Title of host publication2012 Asia-Pacific Microwave Conference, APMC 2012 - Proceedings
Number of pages3
Publication statusPublished - 2012
Event2012 Asia-Pacific Microwave Conference, APMC 2012 - Kaohsiung, Taiwan
Duration: 2012 Dec 42012 Dec 7

Publication series

NameAsia-Pacific Microwave Conference Proceedings, APMC


Other2012 Asia-Pacific Microwave Conference, APMC 2012


  • Multi-modulus frequency divider
  • current mode logic (CML)
  • high-speed prescaler

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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