A 60 GHz CMOS power amplifier with built-in pre-distortion linearizer

Jeng Han Tsai; Chung Han Wu; Hong Yuan Yang; Tian Wei Huang

doi:10.1109/LMWC.2011.2171929

A 60 GHz CMOS power amplifier with built-in pre-distortion linearizer

Jeng Han Tsai^*, Chung Han Wu, Hong Yuan Yang, Tian Wei Huang

^*Corresponding author for this work

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

46 Citations (Scopus)

Abstract

A built-in pre-distortion linearizer using cold-mode MOSFET with forward body bias is presented for 60 GHz CMOS PA linearization on 90 nm CMOS LP process. The power amplifier (PA) achieves a P _sat of 10.72 dBm and OP _{1 dB} of 7.3 dBm from 1.2 V supply. After linearization, the OP _{1 dB} has been doubled from 7.3 to 10.2 dBm and the operating PAE at OP _{1 dB} consequently improves from 5.4% to 10.8%. The optimum improvement of the IMD3 is 25 dB.

Original language	English
Article number	6070991
Pages (from-to)	676-678
Number of pages	3
Journal	IEEE Microwave and Wireless Components Letters
Volume	21
Issue number	12
DOIs	https://doi.org/10.1109/LMWC.2011.2171929
Publication status	Published - 2011 Dec

Keywords

60 GHz
CMOS
linearization
linearizer
power amplifier (PA)
pre-distortion

ASJC Scopus subject areas

Condensed Matter Physics
Electrical and Electronic Engineering

Access to Document

10.1109/LMWC.2011.2171929

Cite this

@article{b4c45572a2bc46d6a1a65b7af13179bd,

title = "A 60 GHz CMOS power amplifier with built-in pre-distortion linearizer",

abstract = "A built-in pre-distortion linearizer using cold-mode MOSFET with forward body bias is presented for 60 GHz CMOS PA linearization on 90 nm CMOS LP process. The power amplifier (PA) achieves a P sat of 10.72 dBm and OP 1 dB of 7.3 dBm from 1.2 V supply. After linearization, the OP 1 dB has been doubled from 7.3 to 10.2 dBm and the operating PAE at OP 1 dB consequently improves from 5.4% to 10.8%. The optimum improvement of the IMD3 is 25 dB.",

keywords = "60 GHz, CMOS, linearization, linearizer, power amplifier (PA), pre-distortion",

author = "Tsai, {Jeng Han} and Wu, {Chung Han} and Yang, {Hong Yuan} and Huang, {Tian Wei}",

note = "Funding Information: Manuscript received November 16, 2010; revised July 30, 2011; accepted October 02, 2011. Date of publication November 07, 2011; date of current version December 07, 2011. This work was supported in part by the National Science Council of Taiwan under Grant NSC 99-2219-E-002-011, Grant NSC 100-2219-E-002-007, Grant NSC 98-2221-E-003-024-MY2, and Grant NSC NSC 100-2221-E-003-027.",

year = "2011",

month = dec,

doi = "10.1109/LMWC.2011.2171929",

language = "English",

volume = "21",

pages = "676--678",

journal = "IEEE Microwave and Wireless Components Letters",

issn = "1531-1309",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "12",

}

TY - JOUR

T1 - A 60 GHz CMOS power amplifier with built-in pre-distortion linearizer

AU - Tsai, Jeng Han

AU - Wu, Chung Han

AU - Yang, Hong Yuan

AU - Huang, Tian Wei

N1 - Funding Information: Manuscript received November 16, 2010; revised July 30, 2011; accepted October 02, 2011. Date of publication November 07, 2011; date of current version December 07, 2011. This work was supported in part by the National Science Council of Taiwan under Grant NSC 99-2219-E-002-011, Grant NSC 100-2219-E-002-007, Grant NSC 98-2221-E-003-024-MY2, and Grant NSC NSC 100-2221-E-003-027.

PY - 2011/12

Y1 - 2011/12

N2 - A built-in pre-distortion linearizer using cold-mode MOSFET with forward body bias is presented for 60 GHz CMOS PA linearization on 90 nm CMOS LP process. The power amplifier (PA) achieves a P sat of 10.72 dBm and OP 1 dB of 7.3 dBm from 1.2 V supply. After linearization, the OP 1 dB has been doubled from 7.3 to 10.2 dBm and the operating PAE at OP 1 dB consequently improves from 5.4% to 10.8%. The optimum improvement of the IMD3 is 25 dB.

AB - A built-in pre-distortion linearizer using cold-mode MOSFET with forward body bias is presented for 60 GHz CMOS PA linearization on 90 nm CMOS LP process. The power amplifier (PA) achieves a P sat of 10.72 dBm and OP 1 dB of 7.3 dBm from 1.2 V supply. After linearization, the OP 1 dB has been doubled from 7.3 to 10.2 dBm and the operating PAE at OP 1 dB consequently improves from 5.4% to 10.8%. The optimum improvement of the IMD3 is 25 dB.

KW - 60 GHz

KW - CMOS

KW - linearization

KW - linearizer

KW - power amplifier (PA)

KW - pre-distortion

UR - http://www.scopus.com/inward/record.url?scp=83555160847&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=83555160847&partnerID=8YFLogxK

U2 - 10.1109/LMWC.2011.2171929

DO - 10.1109/LMWC.2011.2171929

M3 - Article

AN - SCOPUS:83555160847

SN - 1531-1309

VL - 21

SP - 676

EP - 678

JO - IEEE Microwave and Wireless Components Letters

JF - IEEE Microwave and Wireless Components Letters

IS - 12

M1 - 6070991

ER -

A 60 GHz CMOS power amplifier with built-in pre-distortion linearizer

Abstract

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this