A 60 GHz CMOS power amplifier with built-in pre-distortion linearizer

Jeng Han Tsai*, Chung Han Wu, Hong Yuan Yang, Tian Wei Huang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

40 Citations (Scopus)


A built-in pre-distortion linearizer using cold-mode MOSFET with forward body bias is presented for 60 GHz CMOS PA linearization on 90 nm CMOS LP process. The power amplifier (PA) achieves a P sat of 10.72 dBm and OP 1 dB of 7.3 dBm from 1.2 V supply. After linearization, the OP 1 dB has been doubled from 7.3 to 10.2 dBm and the operating PAE at OP 1 dB consequently improves from 5.4% to 10.8%. The optimum improvement of the IMD3 is 25 dB.

Original languageEnglish
Article number6070991
Pages (from-to)676-678
Number of pages3
JournalIEEE Microwave and Wireless Components Letters
Issue number12
Publication statusPublished - 2011 Dec


  • 60 GHz
  • CMOS
  • linearization
  • linearizer
  • power amplifier (PA)
  • pre-distortion

ASJC Scopus subject areas

  • Condensed Matter Physics
  • Electrical and Electronic Engineering


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