A 6-GHz spread spectrum clock generation with EMI reduction of 30.2 dB for SATA-III applications

Hamed Alsuraisry; Jen Hao Cheng; Jian An Lin; Yen Hong Kuo; Jeng Han Tsai; Tian Wei Huang

doi:10.1002/mop.30359

A 6-GHz spread spectrum clock generation with EMI reduction of 30.2 dB for SATA-III applications

Hamed Alsuraisry, Jen Hao Cheng, Jian An Lin, Yen Hong Kuo, Jeng Han Tsai^*, Tian Wei Huang

^*Corresponding author for this work

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

In this letter, a 6-GHz spread spectrum clock generation for Serial AT Attachment Generation 3 (SATA—III) applications in 0.18-pm CMOS technology is presented. The 3rd-order loop filter is to reduce the ripple of control voltage of VCO and the loop bandwidth is 625 KHz. With the aid of second-order delta-sigma (ΔΣ) modulator and triangular profile counter, the division ratio of divider chain can be changed periodically. The modulation frequency is 37.04 KHz with upper bound of 19 for the triangular profile counter. The proposed circuit spreads 30-MHz frequency range from 5.97 to 6.0 GHz with an EMI reduction of 20.3 dB. The dc power consumption is 34 mW with a chip size of 0.54 mm².

Original language	English
Pages (from-to)	622-624
Number of pages	3
Journal	Microwave and Optical Technology Letters
Volume	59
Issue number	3
DOIs	https://doi.org/10.1002/mop.30359
Publication status	Published - 2017 Mar 1

Keywords

CMOS
EMI reduction
SATA
VCO
delta-sigma
spread spectrum

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Atomic and Molecular Physics, and Optics
Condensed Matter Physics
Electrical and Electronic Engineering

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10.1002/mop.30359

Cite this

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title = "A 6-GHz spread spectrum clock generation with EMI reduction of 30.2 dB for SATA-III applications",

abstract = "In this letter, a 6-GHz spread spectrum clock generation for Serial AT Attachment Generation 3 (SATA—III) applications in 0.18-pm CMOS technology is presented. The 3rd-order loop filter is to reduce the ripple of control voltage of VCO and the loop bandwidth is 625 KHz. With the aid of second-order delta-sigma (ΔΣ) modulator and triangular profile counter, the division ratio of divider chain can be changed periodically. The modulation frequency is 37.04 KHz with upper bound of 19 for the triangular profile counter. The proposed circuit spreads 30-MHz frequency range from 5.97 to 6.0 GHz with an EMI reduction of 20.3 dB. The dc power consumption is 34 mW with a chip size of 0.54 mm2.",

keywords = "CMOS, EMI reduction, SATA, VCO, delta-sigma, spread spectrum",

author = "Hamed Alsuraisry and Cheng, {Jen Hao} and Lin, {Jian An} and Kuo, {Yen Hong} and Tsai, {Jeng Han} and Huang, {Tian Wei}",

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AU - Alsuraisry, Hamed

AU - Cheng, Jen Hao

AU - Lin, Jian An

AU - Kuo, Yen Hong

AU - Tsai, Jeng Han

AU - Huang, Tian Wei

PY - 2017/3/1

Y1 - 2017/3/1

N2 - In this letter, a 6-GHz spread spectrum clock generation for Serial AT Attachment Generation 3 (SATA—III) applications in 0.18-pm CMOS technology is presented. The 3rd-order loop filter is to reduce the ripple of control voltage of VCO and the loop bandwidth is 625 KHz. With the aid of second-order delta-sigma (ΔΣ) modulator and triangular profile counter, the division ratio of divider chain can be changed periodically. The modulation frequency is 37.04 KHz with upper bound of 19 for the triangular profile counter. The proposed circuit spreads 30-MHz frequency range from 5.97 to 6.0 GHz with an EMI reduction of 20.3 dB. The dc power consumption is 34 mW with a chip size of 0.54 mm2.

AB - In this letter, a 6-GHz spread spectrum clock generation for Serial AT Attachment Generation 3 (SATA—III) applications in 0.18-pm CMOS technology is presented. The 3rd-order loop filter is to reduce the ripple of control voltage of VCO and the loop bandwidth is 625 KHz. With the aid of second-order delta-sigma (ΔΣ) modulator and triangular profile counter, the division ratio of divider chain can be changed periodically. The modulation frequency is 37.04 KHz with upper bound of 19 for the triangular profile counter. The proposed circuit spreads 30-MHz frequency range from 5.97 to 6.0 GHz with an EMI reduction of 20.3 dB. The dc power consumption is 34 mW with a chip size of 0.54 mm2.

KW - CMOS

KW - EMI reduction

KW - SATA

KW - VCO

KW - delta-sigma

KW - spread spectrum

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A 6-GHz spread spectrum clock generation with EMI reduction of 30.2 dB for SATA-III applications

Abstract

Keywords

ASJC Scopus subject areas

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